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Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN160 SP’08 Power and Energy • Power is drawn from a voltage source attached to the VDD pin(s) of a chip. • Instantaneous Power: P(t ) iDD (t )VDD • Energy: • Average Power: S. Reda EN160 SP’08 T T 0 0 E P(t )dt iDD (t )VDDdt T E 1 Pavg iDD (t )VDD dt T T 0 Dynamic power • Dynamic power is required to charge and discharge load capacitances when transistors switch. • • • • One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND VDD This repeats Tfsw times iDD(t) over an interval of T fsw S. Reda EN160 SP’08 C Dynamic power dissipation Vdd Vin Vout CL load capacitance (gate + diffusion + interconnects) Energy delivered by the supply during input 1 0 transition: Energy stored at the capacitor at the end of 1 0 transition: S. Reda EN160 SP’08 dissipated in NMOS during discharge (input: 0 1) Capacitive dynamic power If the gate is switched on and off f01 (switching factor) times per second, the power consumption is given by For entire circuit where αi is activity factor [0..0.5] in comparison to the clock frequency (which has switching factor of 1) Pdynamic CVDD2 f S. Reda EN160 SP’08 Short circuit current • When transistors switch, both nMOS and pMOS networks may be momentarily ON at once • Leads to a blip of “short circuit” current. • < 10% of dynamic power if rise/fall times are comparable for input and output S. Reda EN160 SP’08 Dynamic power breakup Gate 34% Interconnect 51% Diffusion 15% Total dynamic Power [source: Intel’03] S. Reda EN160 SP’08 Static (leakage) power • Static power is consumed even when chip is quiescent. – Leakage draws power from nominally OFF devices Vgs Vt I ds I ds 0e S. Reda EN160 SP’08 nvT Vds vT 1 e Techniques for low-power design • Reduce dynamic power – – – – Pdynamic CVDD2 f : clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: lowest suitable frequency I1 I2 Clock O1 I3 I4 Enable I5 I 6 Clock Gating S. Reda EN160 SP’08 O2 critical path only reduce supply voltage of non critical gates Dynamic power reduction via dynamic VDD scaling • Scaling down supply voltage Pdynamic CVDD f 2 – reduces dynamic power – reduces saturation current increases delay reduce the frequency Dynamic voltage scaling (DVS): Supply and voltage of the circuit should dynamic adjust according to the workload of criticality of the tasks running on the circuits S. Reda EN160 SP’08 Leakage reduction via adjusting of Vth • Leakage depends exponentially on Vth. How to control Vth? – Remember: Vth also controls your saturation current delay 2. Body Bias 1. Oxide thickness Sol1: statically choose high Vt cells for non critical gates I1 I2 O1 I3 I4 I5 I 6 S. Reda EN160 SP’08 O2 critical path Sol2: dynamically adjust the bias of the body • idle: increase Vt (e.g. by applying –ve body bias on NMOS) • Active: reduce Vt (e.g.: by applying +ve body bias on NMOS) Leakage reduction via Cooling Impact of temperature on leakage current S. Reda EN160 SP’08 Summary We are still in chapter 4: Delay estimation Power estimation Interconnects and wire engineering Scaling theory S. Reda EN160 SP’08