Transcript Slide 1

Design and Implementation of VLSI Systems
(EN01600)
Lecture 19: Combinational Circuit Design (1/3)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2008
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’08
Circuit Families
1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-transistor Circuits
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1. Static CMOS
• Start with network of AND / OR gates
• Convert to NAND / NOR + inverters
• Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y
Y
(a)
(b)
Y
(c)
D
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Y
(d)
Compound gates
• Logical Effort of compound gates
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Input ordering delay effect
– Calculate parasitic delay for Y falling
• If A arrives latest? 2t
• If B arrives latest? 2.33t
2
2
A
2
B
2x
Y
6C
2C
 If input arrival time is known
–Connect latest input to inner terminal
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Asymmetric gates
• Asymmetric gates favor one input over another
• Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input
– So total resistance is same
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gA = 10/9
gB = 2
gavg = (gA + gB)/2 = 14/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
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Symmetric gates
• Inputs can be made perfectly symmetric
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2
2
A
1
1
B
1
1
Y
Skewed gates
• Skewed gates favor one transition over another
• Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
• Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
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Hi- and Lo-Skew
• Definition: Logical effort of a skewed gate for a
particular transition is the ratio of the input
capacitance of the skewed gate to the input
capacitance of an unskewed inverter with equal drive
for the same transition.
• Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
• Logical effort is smaller for favored direction
• But larger for the other direction
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Catalog of skewed gates
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What is the P/N ratio that gives the least
delay?
• We have selected P/N ratio for unit rise and fall resistance (m = 2-3
for an inverter).
• Alternative: choose ratio for least average delay
• By sacrificing rise delay, pMOS transistors can be downsized to
reduced input capacitance, average delay, and total area
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Beware of PMOS
B
4
A
4
Y
1
1
• pMOS is the enemy!
– High input and diffusion capacitance for a given current
• Can we take the pMOS capacitance off the input?
– Various circuit families try to do this…
S. Reda EN160 SP’08