Transcript Slide 1

Design and Implementation of VLSI Systems
(EN0160)
Lecture 20: Circuit Design Pitfalls
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07
How can circuit design go wrong?
• Underestimating different phenomena
• Variations
– Process or runtime
• Reliability concerns
Design for the best and worst and the unexpected in
the future!
[material from subsection 4.7, 4.8 and 6.3]
S. Reda EN160 SP’07
Pitfall 1: Underestimating Leakage
• Circuit
• Symptom
– Latch
f
X
D
Q
f
– Load a 0 into Q
– Set f = 0
– Eventually Q
spontaneously flips to 1
• Principle: Leakage
– Eventually subthreshold leakage may disturb charge
• Solution: Staticize node with feedback
– Or periodically refresh node (requires fast clock, D
not practical processes with big leakage)
f
Q
X
f
f
f
S. Reda EN160 SP’07
Pitfall 2: Underestimating contention due to
transistor ratios
• Circuit
• Symptom
– Pseudo-nMOS OR
X
A
Y
B
– When only one input is
true, Y = 0.
– Perhaps only happens in
SF corner.
• Principle: Ratio Failure
– nMOS and pMOS fight each other.
– If the pMOS is too strong, nMOS cannot pull X low enough.
• Solution: Check that ratio is satisfied in all corners
S. Reda EN160 SP’07
Pitfall 3: Underestimating charge sharing
• Circuit
• Symptom
– Domino AND gate
f
A
Y
Z
X
B
• Principle: Charge Sharing
– Precharge gate while
A = B = 0, so Z = 0
– Set f = 1
– A rises
– Z is observed to
sometimes rise
– If X was low, it shares charge with Y
• Solutions: Limit charge sharing
f
A
B
– Safe if CY >> CX
– Or precharge node X too
S. Reda EN160 SP’07
Y
X
Z
CY
Cx
Pitfall 4: ignoring process variations
Both MOSFETs have 30nm channel with 130
dopant atoms in the channel depletion region
threshold voltage 0.97V
threshold voltage 0.57V
[source: Asenov’99]
Variations are mostly pronounced in gate length,
threshold voltage, and oxide thickness
S. Reda EN160 SP’07
Pitfall 5: ignoring runtime variations
(temperature)
2nd CPU
[source: Devgan’05]
Power 4 server chip
1st CPU
cache
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thermal profile during runtime
Pitfall 5: ignoring runtime variations
(IR drop)
• IR drop/bumps in power supply network reduces saturation
current  larger transistor delay
(deviations in VDD can be by up to 10%)
S. Reda EN160 SP’07
Pitfall 6: ignoring the future (reliability
concerns)
• Electromigration: “Electron wind” causes movement of metal
atoms along wires
– Excessive electromigration leads to open circuits
– Most significant for unidirectional (DC) current: depends on
current density Jdc (current / area)
• Hot Carriers: Electric fields across channel impart high
energies to some carriers
– “hot” carriers blasted into the gate oxide become trapped
→ causes shift in Vt over time
→ Eventually Vt shifts too far for devices to operate
correctly
S. Reda EN160 SP’07
Combat variability by designing your system
in different “corners”
• Transistors have uncertainty in parameters
S. Reda EN160 SP’07
FF
pMOS
SF
TT
FS
SS
slow
• Fast (F)
short
– Leff: ______
– Vt: ______
low
– tox: ______
thin
• Slow (S): opposite
• Not all parameters are independent
for nMOS and pMOS
fast
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
slow
nMOS
fast
Corners for runtime variations
• VDD and T also vary in time and space
• Fast:
high
– VDD: ____
low
– T: ____
S. Reda EN160 SP’07
Corner
F
T
Voltage
1.98
1.8
Temperature
0C
70 C
S
1.62
125 C
Process corners
• Process corners describe worst case
variations
– If a design works in all corners, it will probably
work for any variation.
• Describe corner with four letters (T, F, S)
–
–
–
–
nMOS speed
pMOS speed
Voltage
Temperature
S. Reda EN160 SP’07
Simulate your design at different corners
• Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
S
S
S
S
Power
F
F
F
F
Subthrehold
leakage
F
F
F
S
S. Reda EN160 SP’07