Transcript Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof.

Design and Implementation of VLSI Systems
(EN1600)
Lecture 21: Dynamic Combinational Circuit Design
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2008
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07
Dynamic logic
• Dynamic gates uses a clocked pMOS pullup
• Two modes: precharge and evaluate
2

2/3
A
Y
1
Y
A
Static
1
4/3
Pseudo-nMOS
Y
A
1
Dynamic
• Dynamic circuit operation is divided into two modes:
precharge and evaluate

Y
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Precharge
Evaluate
Precharge
What if the input is ON during precharge?
• What if pulldown network is ON during precharge?
– Contention arises because both pMOS and nMOS will be ON
• Use series evaluation transistor to prevent fight.
precharge transistor



Y
Y
inputs
A
Y
inputs
f
f
foot
footed
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unfooted
Logic effort for dynamic circuits
Very fast with very low logical effort
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Dynamic circuits have a problem:
Monotonicity requirement
violates monotonicity
during evaluation
A

precharge transistor

Precharge
Evaluate
Precharge
Y
A
foot
Y
Output should rise but does not
• Dynamic gates require monotonically rising inputs during
evaluation
–
–
–
–
0→0
0→1
1→1
But not 1 → 0
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Implications of Monotonicity
• But dynamic gates produce monotonically falling outputs during
evaluation
• Illegal for one dynamic gate to drive another!
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Domino Logic
• Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs

Precharge
Evaluate
Precharge
domino AND
W
W
X
Y
Z
X
A
B
C

Y
Z
dynamic static
NAND inverter

A
B
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

W
X
H
C
Y
H
Z
=
A
B

X
C
Z
Domino optimizations
• Each domino gate triggers next one, like a string of dominos
toppling over
• Gates evaluate sequentially but precharge in parallel
• Thus evaluation is more critical than precharge
• HI-skewed static stages can perform logic

S0
S1
S2
S3
D0
D1
D2
D3
H
Y

S4
S5
S6
S7
D4
D5
D6
D7
8-input multiplexer built from two 4-input dynamic multiplexers
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Dual-Rail Domino
• Domino only performs noninverting
functions:
– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs
sig_h
sig_l
Meaning
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid
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Leakage problems
• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper

A
1 k
2
2
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X
H
Y
Charge sharing
• Dynamic gates suffer from charge sharing


A
B=0
Y
CY
x
Cx
A
Y
Charge sharing noise
x
• Solution: add secondary precharge transistors
• Typically need to precharge every other node
• Big load capacitance CY helps as well

Y
A
B
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x
secondary
precharge
transistor
Domino Summary
• Domino logic is attractive for high-speed circuits
– 1.5 – 2x faster than static CMOS
– But many challenges: Monotonicity, leakage, charge sharing,
noise, and high dynamic power
• Widely used in high-performance microprocessors
Circuit Families





Static CMOS
Ratioed Circuits
Cascode Voltage Switch Logic
Pass-transistor Circuits
Dynamic Circuits
S. Reda EN160 SP’07