Transcript Slide 1

Design and Implementation of VLSI Systems
(EN0160)
Lecture 11: Logical Effort (1/2)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07
Last lecture: delay estimation
We calculated Rise and Fall delays
Q: What happens if we decide to scale the transistors by factor k?
S. Reda EN160 SP’07
Impact of transistor sizing
What happens to delay?
Is it the case that increasing the size of the transistor always reduces
delay?
S. Reda EN160 SP’07
Impact of sizing in a path
×K
Cout
Less output resistance; increase output capacitance
→ delay reduces (parasitic delay stays the same)
Larger input capacitance
→ increases delay of previous stage!
What is the final outcome? Should we size? By how much?
S. Reda EN160 SP’07
Remember gate design
2
2
2
2
3
3
3
2
2
3
5C
3
5C
5C
3
9C
3C
3C
If you decide to increase everything by a factor of k
Unloaded delay =3RC
How about an inverter?
 12 ps in 180 nm process
40 ps in 0.6 mm process
S. Reda EN160 SP’07
Expressing delay as a linear model
“normalized
delay”
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Summary of linear delay model
• g: logical effort = ratio between input
capacitance of the gate size to the input
capacitance of the inverter that would
deliver the same current
• h: electric effort = ratio between load
capacitance and the gate input
capacitance (sometimes called fanout)
• p: parasitic delay
• represents delay of gate driving no load
• set by internal parasitic capacitance
S. Reda EN160 SP’07
Computing logical effort
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Computing parasitic delay
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Example: Ring oscillator
• Estimate the frequency of an N-stage ring oscillator
Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:
Frequency:
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g=
h=
p=
d=
fosc =
Example: Ring oscillator
• Estimate the frequency of an N-stage ring oscillator
Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:
Frequency:
S. Reda EN160 SP’07
31 stage ring oscillator in
g=1
0.6 mm process has
h=1
frequency of ~ 200 MHz
p=1
d=2
fosc = 1/(2*N*d) = 1/4N
Example: FO4 Inverter
• Estimate the delay of a fanout-of-4 (FO4) inverter
d
Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:
S. Reda EN160 SP’07
g=
h=
p=
d=
Example: FO4 Inverter
• Estimate the delay of a fanout-of-4 (FO4) inverter
d
Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:
S. Reda EN160 SP’07
g=1
h=4
p=1
d=5
The FO4 delay is about
200 ps in 0.6 mm process
60 ps in a 180 nm process
f/3 ns in an f mm process