Reconfigurable Computing (EN2911X, Fall07) Lecture 15: SystemC (3/3) Prof. Sherief Reda Division of Engineering, Brown University http://ic.engin.brown.edu

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Integer data types

• Supported native C++ synthesizable data types – long long (64 bits) – long (32 bits) – int (32 bits) – short (16 bits) – char (8 bits) – bool (1 bit) • SystemC also allows further refined storage types – sc_bit – sc_bv – sc_int <width> – sc_uint <width> – sc_bigint <width> – sc_biguint <width> Reconfigurable Computing S. Reda, Brown University

Floating-point data types • Full supported for compilation with VisualC++ and systemC library • Supported for synthesis by Celoxica’s Agility compiler only if they can be evaluated during compilation time → Any calculation involving float point must evaluate to a constant Synthesizable example sc_int<16> SinTable [128]; for(int i=0; i < 128; i++ ) { double index=(double) i; double angle=2.0*PI*(index/128.0); double sineangle=sin(angle); SineTable[i]=sc_uint<16>(sineangle*32767.0); } Not synthesizable example sc_in in; float x; X=in.read(); Reconfigurable Computing S. Reda, Brown University

Arrays • Full supported for compilation with VisualC++ and systemC library • For synthesis with Agility compiler, an array is synthesizable if its elements are of a synthesizable type and its size is compile-time determinable Synthesizable example Although the array is not synthesizable, the members are only used during compilation time and are cat to type int int temp, array[100]; sc_in in; For(int y=0; y < 100; y++) { in.read(temp); array[y]=temp; wait(); } #include float l[10]; for(int y=0; y<10; y++) l[y]=log10((y+1)*10); //… sc_out out; for(int y=0; y < 10; y++) out.write((int)l[y]); Reconfigurable Computing S. Reda, Brown University

Pointers • Full supported for compilation with VisualC++ and systemC library • Agility supports pointers subject to the restriction that Agility can always determine the target of the pointer • A pointer is synthesizable if it is a pointer to a synthesizable type, and the value to which the pointer points is compile-time determinable Resolvable pointer void clear(char *a, char *b) { *a=255; *b=255; } } sc_out out; unsigned char x, y; clear(&x, &y); out.write(x); Reconfigurable Computing S. Reda, Brown University

Other considerations for synthesis • Full supported for compilation with VisualC++ and systemC library • Operator new is supported at compiler time but not at runtime.

• delete operator is not supported • Each action in a switch must have a break statement. Fall through is not allowed • If a function to be synthesized, its body must only contain code that within Agility synthesizable subset • General recursion is not supported for synthesis Reconfigurable Computing S. Reda, Brown University

Example using synthesis and compilation flow Synthesizable subset Celoxica agility synthesizer Verilog/edif Quartus II Rest of code (testbenches, SW code) SystemC library Visual C++ executable Reconfigurable Computing S. Reda, Brown University

Celoxica’s Agility compiler tutorial Reconfigurable Computing S. Reda, Brown University

Starting adding files to your project Reconfigurable Computing S. Reda, Brown University

Adjust the project settings to use the Cyclone II devices Reconfigurable Computing S. Reda, Brown University

Add your file and write your class declaration Reconfigurable Computing S. Reda, Brown University

Add the main synthesis entry point Reconfigurable Computing S. Reda, Brown University Not the most direct implementation

Build your project Reconfigurable Computing S. Reda, Brown University

Check the CDFG and Verilog output Reconfigurable Computing S. Reda, Brown University

Copy the Verilog file into Quartus II Sometimes the Celoxica compiler changes the name of input/output outputs when it exports to Verilog so make sure to fix this in Quartus II assignment editor Then build and download to the FPGA Reconfigurable Computing S. Reda, Brown University

What if we want to verify and simulate before downloading to the FPGA?

Choose Visual C++ Add a tester.h for tester module clk

tester

KEY[0] KEY[1]

orgate

LEDG Reconfigurable Computing S. Reda, Brown University

Add the main body Reconfigurable Computing S. Reda, Brown University

Hit Build and then run the executable Build indirectly invokes the command line compiler of VC (cl) which links your compiled code with SystemC.lib

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If you like to synthesis again, make sure to mark the files you want to synthesize Choose Verilog as your desired output again Exclude tester.h and orgate_exe.cpp

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HW/Lab 3 •Objective: Learn SystemC using both the synthesis and compilation flows.

•This time it is a simple example. We will design an 8-bit ALU. Use the 18 switches in the DE2 board to achieve your target: – 8 switches give the binary of the first unsigned integer – 8 switches give the binary of the second unsigned integer – 2 switches give the ALU operation (addition, subtraction, multiplication and XORING) •In your report, make sure to include the SystemC code, the executable output print of simulations, and the FPGA resource utilization. You have to send me by email your projects archived for both the SystemC design and the Quartus II files •Lab due before Thanksgiving holiday (Thur 22 nd ) •Tutorials and Celoxica manual uploaded at the class webpage and also available to download from Engineering website Reconfigurable Computing S. Reda, Brown University