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Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN160 SP’07 Impact of doping on silicon resistivity silicon 4.9951022 atoms in cm3 Resistivity 3.2 105 Ωcm dope with phosphorous or arsenic n-type 1 atom in billion 88.6 Ωcm 1 atom in million 0.114 Ωcm 1 atom in thousand 0.00174 Ωcm dope with boron p-type 1 atom in billion 266.14 Ωcm 1 atom in million 0.344 Ωcm 1 atom in thousand 0.00233 Ωcm Electrons are more mobile/faster than holes S. Reda EN160 SP’07 Use P and N material to make diodes and transistors and gates Source Gate A Drain Polysilicon SiO2 Al p n B n+ n+ p S. Reda EN160 SP’07 bulk Si One-dimensional representation Layouts versus stick diagrams S. Reda EN160 SP’07 IC manufacturing Spin resist Expose (using mask) Develop resist ACTION (e.g., implant) Remove Resist S. Reda EN160 SP’07 The MOS transistor has three regions of operation • Cut off Vgs < Vt • Linear (resistor): Vgs > Vt & Vds < Vgs-Vt Current α Vds NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V • Saturation: Vgs > Vt and Vds ≥ Vgs-Vt Current is independent of Vds 0 V I ds Vgs Vt ds 2 2 V V gs t 2 S. Reda EN160 SP’07 Vgs Vt V V V ds ds dsat Vds Vdsat cutoff linear saturation Non-ideal Shockley vs actual operation Channel length modulation: Increasing Vds decreases channel length increases current Velocity saturation: At high electric field, drift velocity rolls off due to carrier scattering Temperature dependency S. Reda EN160 SP’07 Inverter voltage transfer characteristics A B C D S. Reda EN160 SP’07 E CMOS inverter noise margins desired regions of operation V out V in S. Reda EN160 SP’07 Simple RC delay models • Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C • Capacitance proportional to width • Resistance inversely proportional to width d g d k s kC R/k kC 2R/k g g kC kC s S. Reda EN160 SP’07 s d k s kC g kC d Elmore delay model • ON transistors look like resistors • Pullup or pulldown network modeled as RC ladder • Elmore delay of RC ladder t pd R i to source Ci nodes i R1C1 R1 R2 C2 ... R1 R2 ... RN CN R1 S. Reda EN160 SP’07 R2 R3 C1 C2 RN C3 CN Logical effort to calculate gate delay • g: logical effort = ratio between input capacitance of the gate to that of an inverter than would deliver the same current • h: electric effort = ratio between load capacitance and the gate input capacitance (sometimes called fanout) • p: parasitic delay • represents delay of gate driving no load • set by internal parasitic capacitance S. Reda EN160 SP’07 Effort of Multistage logic networks 10 g1 = 1 h1 = x/10 x g2 = 5/3 h2 = y/x y g3 = 4/3 h3 = z/y z g4 = 1 h4 = 20/z 20 • Logical effort generalizes to multistage networks • Path Logical Effort • Path Electrical Effort • Branching factor b • Path Effort F=GBH S. Reda EN160 SP’07 G gi H Cout-path Cin-path Con path Coff path Con path B bi Optimization using logical effort models Delay of multi-stage network is minimized when each stage bears the same effort Optimal number of stages D NF 1 N n1 pi N n1 pinv i 1 1 1 D N N F ln F F pinv 0 N 1 N F pinv 1 ln 0 S. Reda EN160 SP’07 1 N Power • Dynamic • Short circuit power (dynamic) • Static (leakage) Vgs Vt I ds I ds 0e nvT Vds vT 1 e Techniques to reduce power: clock gating, multiple Vdd, multiple Vt, temperature, S. Reda EN160 SP’07 Interconnects They have resistance and capacitance → contribute to delay and dynamic power Distributed vs lumped Elmore delay model How to calculate delay (gate + wires)? S. Reda EN160 SP’07 Interconnects Coupling capacitance introduces cross talk which depends on the switching activity of the neighboring wires. Cross talk increases delay and causes noise Solutions to interconnect problems 1. Width, Spacing, Layer 2. Shielding 3. Repeater insertion 4. Wire staggering and differential signaling 5. Buffer insertion (what are the locations/optimal number?) 6. Staggering and differential signaling S. Reda EN160 SP’07 Implications of ideal device scaling devices S. Reda EN160 SP’07 interconnects Logic families • Asymmetric gates (favors one input) • Skewed gates (favors one transition) • How to calculate logical effort? Families to get rid of some of static CMOS problems: help in one way, introduces another problem domino AND en Y A B C domino CPTL W X A B C Pseudo-NMOS (ratioed circuits) dynamic static NAND inverter S A PTL VDD M2 F S M1 Cascode Voltage Switch Level B S S. Reda EN160 SP’07 Y Z Circuit Design Pitfalls fast variations FF pMOS SF TT FS slow SS slow nMOS fast Design in corners make sure you have enough margins S. Reda EN160 SP’07