Transcript Slide 1
Design and Implementation of VLSI Systems (EN1600) Lecture 30: Array Subsystems (DRAM/ROM) Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN1600 SP’08 Lecture outline • Last time – Memory periphery (row/column circuitry) – Core cell: SRAM cells • This time (different core cells) – DRAM cells – ROM cells – Non Volatile Read Write (NVRW) cells S. Reda EN1600 SP’08 3T DRAM cell WWL WWL RWL write Vdd BL1 M3 M1 X M2 Cs BL1 BL2 X Vdd-Vt RWL read BL2 Vdd-Vt No constraints on device sizes (ratioless) Reads are non-destructive Value stored at node X when writing a “1” is VWWL - Vtn S. Reda EN1600 SP’08 V 1T DRAM Cell WL WL M1 CBL X X write “1” read “1” Vdd-Vt Cs BL Vdd/2 Vdd sensing BL Write: Cs is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between CBL and Cs Read is destructive, so must refresh after read Leakage cause stored values to “disappear” → refresh periodically S. Reda EN1600 SP’08 The bit line is precharged to VDD/2 S. Reda EN1600 SP’08 How DRAM cells are manufactured? Trench capacitor S. Reda EN1600 SP’08 DRAM subarray architectures rejects common mode noise sensitive to noise S. Reda EN1600 SP’08 ROMs • Read-Only Memories are nonvolatile – Retain their contents when power is removed • Mask-programmed ROMs use one transistor per bit – Presence or absence determines 1 or 0 S. Reda EN1600 SP’08 NOR ROMs • 4-word x 6-bit ROM – Represented with dot diagram – Dots indicate 1’s in ROM weak pseudo-nMOS pullups A1 A0 Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 2:4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nMOS NORs S. Reda EN1600 SP’08 Dot diagram NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] • All word lines high by default with exception of selected row • No transistor with the selected word -> bitline pulled down • Transistor with the selected word -> bitline remain high S. Reda EN1600 SP’08 Non Volatile Read/Write (NVRW) memories • Same architecture as ROM structures • A floating transistor gate is used • similar to traditional MOS, except that an extra polysilicon strip is inserted between the gate and channel • allow the threshold voltage to be progammable Floating gate Gate Source D Drain G tox tox n+ p n+_ S Substrate Device cross-section S. Reda EN1600 SP’08 Schematic symbol Floating gate transistor programming 20 V 10 V S 5V 20 V D Avalanche injection Process is self-timing - Effectively increases Threshold voltage S. Reda EN1600 SP’08 5V 0V -5V S 0V D Removing programming voltage leaves charge trapped - 2.5 V S 5V D Programming results in higher V T . Floating gate is surrounded by an insulator material traps the electrons Flash Electrically Erasable ROMs Control gate Floating gate erasure n 1 source Thin tunneling oxide programming n 1 drain p-substrate To erase: ground the gate and apply a 12V at the source S. Reda EN1600 SP’08 Basic Operations in a NOR Flash Memory― Erase S. Reda EN1600 SP’08 Basic Operations in a NOR Flash Memory― Write S. Reda EN1600 SP’08 Basic Operations in a NOR Flash Memory― Read S. Reda EN1600 SP’08