Transcript The Design of Survivable Networks

ECEN 248: INTRODUCTION TO
DIGITAL SYSTEMS DESIGN
Lecture 13
Dr. Shi
Dept. of Electrical and Computer Engineering
SEQUENTIAL CIRCUITS: LATCHES
Overview


Circuits require memory to store intermediate data
Sequential circuits is a circuit that has memory
 Flip-flop
and latch
 Static Random Access Memory (SRAM)
 Dynamic Random Access Memory (DRAM)

Sequential circuits use a clock signal to determine
when to store values.
The story so far ...

Combinational circuits


No way of remembering or storing information after
inputs have been removed.
To handle this, we need sequential logic capable of
storing intermediate (or final) results.
Sequential Circuits
Inputs
Outputs
Combinational
circuit
Flip Flops
Next
state
Clock
Clock: a periodic external signal
synchronizes when states change
makes it easier to design and build large systems
Present
state
Cross-coupled Inverters



The system has two stable states
A stable value can be stored at inverter outputs
Not possible to set a desired state
State 0
State 1
Cross-coupled Inverters (cont.)
•
This circuit has no stable states
Y
Z
X
X Y
X Y  Z  X  X
Y Z
ZX
'1'
X
'0'
Y
Z
0

2
3
4
5
6
7
8
9
10
11
Time
SR Latch
S-R Latch with NORs
R (reset)
S (set)

Q
S
R Q
Q’
Q
1
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
S-R latch made from cross-coupled NORs
 If Q = 1, set state
 If Q = 0, reset state
set
reset

Forbidden
Set
Reset
Stable
S
R
S=1 and R=1 generates unpredictable results
Q
Q
S-R Latch with NORs
R (reset)
S (set)
S
R
Q
Q
t pd
Q
S
R Q
Q’
Q
1
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
Forbidden
Set
Reset
Stable
S-R Latch with NORs
R (reset)
S (set)


Q
S
R Q
Q’
Q
1
1
0
0
1
0
1
0
0
0
1
1
0
0
1
0
0
1
Forbidden
Set
Reset
Stable
What happens if both inputs R and S simultaneously
change from 0 to 1?
Race conditions: See who runs faster
S-R Latch with NANDs
S
R
S
Q
Q’
0
0
1
1
R
0
1
0
1
Latch made from cross-coupled NANDs
Sometimes called S’-R’ latch
Usually S=1 and R=1
S=0 and R=0 generates unpredictable results
Q
1
1
0
0
1
Q’
1 Forbidden
0 Set
1 Reset
1
0 Store
S-R Latches
NOR S-R Latch with Control Input
Latch is level-sensitive, in regards to C
Only stores data if C’ = 0
R’
Q
C’
Latch operation
enabled by
S’
Q’
C
Input sampling
enabled by gates
Outputs change when C
is low:
RESET and SET
Otherwise: HOLD
S-R Latch with control input
Occasionally, desirable to avoid latch changes
C = 0 disables all latch state changes
Control signal enables data change when C = 1
Right side of circuit same as ordinary S-R latch.
D-Latch
D Latch
Q0 indicates the previous state (the previously stored value)
X
S
D
Q
C
Q’
R
Y
D
0
1
X
C
Q Q’
1
1
0
0 1
1 0
Q0 Q0’
X Y
C Q Q’
0
0
1
1
X
1
1
1
1
0
0
1
0
1
X
Q0
0
1
1
Q0
Q0’
1
0
1
Q0’
Store
Reset
Set
Disallowed
Store
D Latch
X
D
S
Q
C
Q’
Y
D
C Q Q’
0
1
X
1
1
0
R
0 1
1 0
Q0 Q0’
Input value D is passed to output Q when C is high
Input value D is ignored when C is low
D Latch
Latches on following
edge of clock
E
x
D
Q
z
E
x
C
z
The D latch stores data indefinitely, regardless of input D values, if
C=0
Forms basic storage element in computers
Symbols for Latches
SR latch is based on NOR gates
S’R’ latch based on NAND gates
D latch can be based on either.
D latch sometimes called transparent latch
Disadvantage of Transparent Latches
D
D
G
G
Q
D
G
Q
D
Q
Q
G
Problems:
When G=1, D passes through the entire chair
When G=1, any glitches of D passes through the entire circuit
Master-Slave D Flip Flop
Consider two latches combined together
Only one C value active at a time
Output changes on falling edge of the clock
always @(negedge clk)
begin Q=D; end
D
C
Q
Q’
0
1
X
1
1
0
0 1
1 0
Q0 Q0’
Positive and Negative Edge D
Flip-Flop
D flops can be triggered on positive or negative edge
Bubble before Clock (C) input indicates negative edge trigger
Lo-Hi edge
Hi-Lo edge
Clocked D Flip-Flop
Stores a value on the positive edge of C
Input changes at other times have no effect on output
T Flip-Flop
Positive Edge-Triggered T Flip-Flop
Created from D flop
T=0 -> keep current
K resets
T=1 -> invert current
T
0
1
C
Q
Q’
Q0 Q0’
Q’0 Q0
JK Flip-Flop
Positive Edge-Triggered J-K Flip-Flop
Created from D flop
D = JQ’+K’Q
J sets
K resets
J=K=1  invert output
J
0
0
1
1
K
0
1
0
1
CLK
Q Q’
Q0 Q0’
0
1
1
0
TOGGLE
Clocked J-K Flip Flop
Two data inputs, J and K
J -> set, K -> reset, if J=K=1 then toggle output
Characteristic Table
Asynchronous Inputs
Asynchronous Behavior
• Synchronous behavior
• Effects on the output are synchronized with the CLK input.
• Asynchronous behavior
• Effects on the output are synchronized with the CLK.
•Only used for set/reset
Asynchronous Inputs
Asynchronous Inputs
• Note reset signal (R) for
D flip flop
• If R = 0, the output Q is
cleared
•This event can occur at
any time, regardless of the
value of the CLK
Summary

Flip flops are powerful storage elements
 They



D flip flop is simplest and most widely used
Asynchronous inputs allow for clearing and presetting
the flip flop output
Multiple flops allow for data storage
 The


can be constructed from gates and latches!
basis of computer memory!
Combine storage and logic to make a computation
circuit
Next time: Analyzing sequential circuits.