Transcript Lecture No. 3

Sequential Circuits
• Sequential Circuits
– Digital circuits that use memory elements as
part of their operation
– Characterized by feedback path
– Outputs depend not only on its current inputs
but also on the past sequence of inputs, possibly
arbitrarily far back in time
• Examples
– Counters
– Parallel-to-Serial conversion of byte data
1
Q
Sequential Circuits
• State of Circuit
– Binary information stored in the memory
Q circuit
elements determines the “state” of the
– Output and next state is determined by input
signals and current state of circuit
2
Q
Sequential Circuits
• 2 Major Types of Circuits
• Asynchronous
Q
– Inputs may change at any time
– Complicated and maybe unstable because of
feedback
• Synchronous
– Input change is only effected at certain times
determined by a master clock (pulse or edge
detection) or master-slave operation
3
Asynchronous Sequential Circuits
Latch
• Temporary storage device that has two stable
states
• Normally has two inputs
• Two complementary outputs available: Q and Q’
• When the latch is set to a certain state it retains its
state unless the inputs are changed to set the latch
to a new state
• A latch serves as a memory element which is able
to retain the information stored in it
4
S-R (Set-Reset) Latch
R
S
1
Q
2
Q
Input
S
0
0
1
1
R
0
1
0
1
Output
Qt+1
Qt
0
1
Invalid
5
S-R (Set-Reset) Latch
Truth table
Q
S
R
Qt+1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
Invalid
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
Invalid
Characteristic Equation
Qt+1 = S + R’Q;
SR = 0
6
S-R (Set-Reset) Latch
S
1
Q
2
Q
R
Input
S’
1
1
0
0
R’
1
0
1
0
Output
Qt+1
Qt
0
1
Invalid
7
S-R (Set-Reset) Latch
Standard Logic Symbols
S
Active-low
Input
Q
S
Q
S-R
Latch
S-R
Latch
R
Active-high
Input
Q R
Q
8
S-R (Set-Reset) Latch
Timing diagram of active-low input latch
S
R
Q
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10 t11 t12
9
S-R (Set-Reset) Latch
Timing diagram of active-high input latch
S
R
Q
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10 t11 t12
10
S-R Latch Apps - Burglar Alarm
+5 v
Alarm
switch
S
R
Reset
switch
Alarm
Active-low
Input
Q
S-R
Latch
Q
11
Synchronous Sequential Circuits
• Latches
– Asynchronous circuits
– Outputs are transparent to inputs
• Gated or Clocked Latches
– Synchronous circuits b/c clock or enable input dictates
when inputs are latched onto outputs
– May still have both transparent and latched operation if
inputs change while clock is active
• Flip Flops
– Flip-Flops are synchronous bi-stable devices, known as
bi-stable multivibrators
– The output of the flip-flop can only change once by the
applied inputs upon application of clock input
12
– Edge Triggered or Master Slave
S-R Gated Latch
– Adds a clock (control) input gated to an S-R latch
– S/R inputs are passed on to the latch portion
synchronised by the clock pulse
– Also called Clocked S-R Latch
S
3
1
Q
EN
CK
CK
4
R
S
2
Q
Q
Gated
S-R
Latch
R
Q
13
S-R Gated Latch
Truth table
Q
S
R
Qt+1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
Invalid
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
Invalid
Characteristic Equation
Qt+1 = S + R’Q;
SR = 0
14
S-R Gated Latch Timing
S
R
CK
Q
t1
t2
t3
t4
t5
t6 t7
t8
15
D Gated Latch
D
3
1
Q
4
2
Q
CK
EN
16
D Gated Latch
Truth table
Q
D
Qt+1
0
0
0
0
1
1
1
0
0
1
1
1
Characteristic Equation
Qt+1 = D
17
D Gated Latch Apps
0
1
1
1
0
0
1
0
1
D
EN
D
EN
D
EN
D
EN
D
EN
D
EN
D
EN
D
EN
Q
Q
Q
Q
Q
Q
Q
Q
1
1
1
0
0
1
0
1
I0
EN
Y
Serial
Transmission
Line
I1
74X151
I2
I3
I4
A0
I5
A1
I6
A2
I7
Counter
C2
clock
C1
C0
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D Gated Latch Timing
D
CLK
Q
t1
t2
t3
t4
t5
t6
t7
t8
t9
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Latches - Transparency Problem
• What’s transparency?
– Output follows input instantaneously –
tunneling
– Behavior depicted in latches
• The transparency problem
– If output is fed back, circuit may become
unstable
• The solution?
– Master Slave or Edge Triggered FF
20
Transparency Problem
21
Transparency Problem
22
Master Slave Flip Flop
23
Master Slave Flip Flop
24
S-R Master Slave Flip Flop
25
Master Slave Flip Flops Summary
•
•
•
•
Have two stages – Master and Slave
Each stage works in one half of the clock signal
Inputs are applied in the first half of the clock signal
Outputs do not change until the second half of the clock
signal
• Allows digital circuits to operate in synchronization with a
common clock signal
• Inherently slow throughput
• Mostly obsolete
Better Solution:
• Edge Triggered flip-flops
• An edge-triggered flip-flop ignores the pulse while it is at
a constant level and triggers only during a transition of the
clock signal - faster
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D Flip-Flop Apps – Registers
D0
D
SET
Q
Q0
D0
D1
D
SET
CLR
D2
D
SET
CLR
D3
D
SET
Q
Q
D1
Q1
Q
Q
Q2
Q
Q
Q3
Connected to inputs of Multiplexer
CLR
D2
D3
CLK
Q0
Q1
Q2
CLK
Q3
CLR
Q
t1
27
Edge Triggered J-K Flip Flop
J
3
1
Q
4
2
Q
CLK
K
28
Edge Triggered J-K Flip Flop
J
Q
J-K
Flip-Flop
CLK
J
Q
J-K
Flip-Flop
CLK
K
Q
Input
K
Qt
Output
Q
Input
Output
CLK
J
K
Qt+1
CLK
J
K
Qt+1
0
X
X
Qt
0
X
X
Qt
1
X
X
Qt
1
X
X
Qt
↑
0
0
Qt
↓
0
0
Qt
↑
0
1
0
↓
0
1
0
↑
1
0
1
↓
1
0
1
↑
1
1
Qt’
↓
1
1
Qt’
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T Flip Flop
Truth table
Q
T
Qt+1
0
0
0
0
1
1
1
0
1
1
1
0
Characteristic Equation
Qt+1 = TQ’ + T’Q
30
T Flip Flop
T
CLK
Q
t1
t2
t3
t4
t5
t6
t7
t8
t9
31
Flip-Flop Operating Characteristics
• Performance specified by several operating
characteristics provided in the data sheets of FF’s
• The important operating characteristics are:
–
–
–
–
–
–
Propagation Delay
Set-up Time
Hold Time
Maximum Clock frequency
Pulse Width
Power Dissipation
32
Flip Flop Logic Symbols Summary
33
Flip Flop Characteristic Equations
Qt+1 = S + R’Q; SR = 0
Qt+1 = D
Qt+1 = JQ’ + K’Q
Qt+1 = TQ’ + T’Q
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Flip Flop Excitation Tables
Qt Qt+1
0
0
0
1
1
0
1
1
S
0
1
0
X
R
X
0
1
0
Qt Qt+1
0
0
0
1
1
0
1
1
D
0
1
0
1
Qt Qt+1
0
0
0
1
1
0
1
1
J
0
1
X
X
K
X
X
1
0
Qt
0
0
1
Qt+1
0
1
0
T
0
1
1
1
1
0
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Flip Flop Usage Guide
Type of Application
Transfer of data
(e.g. shift registers)
Complementation
(e.g. binary counters)
Above or any other
general application
Preferred FF
RS or D
T
JK
36