Transcript EET 251 Unit 2 - Sinclair Community College

EET 1131 Unit 10
Flip-Flops and Registers

Read Kleitz, Chapter 10.

Exam #2 next week.


Homework #10 and Lab #10 due in
1.5 weeks.
Quiz in 1.5 weeks.
Combinational Logic versus Sequential
Logic


A combinational logic circuit is a
circuit whose output depends only on
the circuit’s present inputs. (“Has no
memory of the past.”)
A sequential logic circuit is a circuit
whose output may depend on the
circuit’s previous states as well as its
present inputs. (“Has a memory.”)
Five Latches and Flip-flops

Our textbook refers to all five of these as
“flip-flops,” but most people call three of
them “latches” and two of them “flip-flops.”
Name
Section in Textbook
Textbook’s
name for it
Sample
Chips
S-R latch
10-1
S-R flip-flop
Gated S-R latch
10-2
Gated S-R flip-flop
Gated D-latch
10-3 and 10-4
Gated D flip-flop
7475
D flip-flop
10-5
D flip-flop
7474
J-K flip-flop
10-6 (obsolete masterslave variety; ignore it)
10-7 (modern edgetriggered variety)
74279
7476
J-K flip-flop
74LS76
Latches
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory that stores a
single bit.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs.
R
S
Q
Q
NOR S-R Latch
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
S-R Latch
The S-R latch is in a stable (latched) condition when both
inputs are LOW.
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (0). To SET the latch
(Q = 1), a momentary HIGH signal
is applied to the S input while the R
remains LOW.
To RESET the latch (Q = 0), a
momentary HIGH signal is
applied to the R input while the S
remains LOW.
0 R
1
0
10
0 S
0 R
1
0
1
0
0 S
Q
Latch
initially
RESET
Q
Q
Latch
initially
SET
Q
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Truth-Table for S-R Latch (active-high inputs)
S
R
Q
0
0
Q0
Q0
0
1
0
1
RESET
1
0
1
0
SET
1
1
0
0
Invalid state
Q
Comments
No change.
Truth-Table for Gated S-R Latch
(active-high inputs)
EN S
0
1
1
1
1
X
0
0
1
1
R
Q
X
0
1
0
1
Q0
Q0
0
1
0
Q
Q0
Q0
1
0
0
Comments
No change
No change
RESET
SET
Invalid state
Gated S-R Latch
A gated S-R latch is a variation on the basic S-R latch.
S
The gated latch has an additional
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with
Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R have effect only when EN is HIGH.
S
R
EN
Q
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Gated D-Latch
The gated D latch is similar to the gated S-R latch but
combines the S and R inputs into a single D input as
shown:
D
Q
EN
D
Q
EN
Q
Q
A simple rule for the gated D latch is:
Q follows D when the Enable is active.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Gated D-Latch
The truth table for the gated D latch summarizes its
operation. If EN is LOW, then there is no change in the
output and it is latched.
Inputs
Outputs
D
EN
Q
Q
Comments
0
1
X
1
1
0
0
1
Q0
1
0
Q0
RESET
SET
No change
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Gated D-Latch
D
Q
EN
Determine the Q output for the gated
D latch, given the inputs shown.
Q
D
EN
Q
Notice that the Enable is not active during these times, so
the output is latched.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Two Popular Latch Chips
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
74279 (Quad active-low S-R latch)
7475 (Quad Gated D latch)
Level-Triggered versus EdgeTriggered


Gated S-R latches and gated D latches
are often called level-triggered
devices, because the output can
change any time the enable input is at
the correct level (HIGH or LOW).
Other devices, such as flip-flops, are
edge-triggered, because the output
can only change when there is a rising
or falling edge on the clock input.
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D
Q
C
Dynamic
input
indicator
D
Q
C
Q
(a) Positive edge-triggered
Rising edge-triggered
Leading edge-triggered
Q
(b) Negative edge-triggered
Falling edge-triggered
Trailing edge-triggered
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
The truth table for a positive-edge triggered D flip-flop
shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.
Inputs
D
1
0
CLK
Outputs
Inputs
Q
Q
Comments
D
1
0
0
1
SET
RESET
1
0
(a) Positive-edge triggered
CLK
Outputs
Q
Q
Comments
1
0
0
1
SET
RESET
(b) Negative-edge triggered
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
The J-K flip-flop is more versatile than the D flip flop. In
addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states
(toggles) on the active clock edge (in this case, the rising
edge).
Inputs
J K
Outputs
CLK
Q
Q
Comments
No change
RESET
SET
Toggle
0
0
1
0
1
0
Q0
0
1
Q0
1
0
1
1
Q0
Q0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
Q
J
CLK
Determine the Q output for the J-K
flip-flop, assuming Q is initially high.
K
Q
Notice that the outputs change on the rising edge of the clock.
Set
Toggle
Set
Latch
CLK
J
K
Q
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flops
Synchronous inputs (for example the D or J-K inputs)
affect the output on the triggering edge of the clock. Most
flip-flops also have other inputs that are asynchronous,
meaning they affect the output independent of the clock.
PRE
Two such inputs are normally labeled
PRE (preset) and CLR (clear). These
inputs are usually active LOW, as
shown here.
J
Other common names for these pins are
SET and RESET.
K
Q
CLK
Q
CLR
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
PRE
Flip-flops
Q
J
CLK
Determine the Q output for the J-K
flip-flop, assuming Q is initially high.
Q
K
CLR
Set
Toggle
Set
Reset
Toggle
Latch
CLK
J
K
PRE
Set
Reset
CLR
Q
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Two Popular Flip-Flop Chips


7474 (Dual D Flip-Flop)
74LS76 (Dual J-K Flip-Flop)
Flip-flop Timing Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge
CLK
CLK
Q
50% point on LOW-toHIGH transition of Q
tPLH
50% point
50% point on HIGH-toLOW transition of Q
Q
tPHL
The typical propagation delay time for the 74AHC family (CMOS) is
4 ns. Even faster logic is available for specialized applications.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Timing Characteristics
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.
PRE
50% point
50% point
Q
tPHL
CLR
50% point
50% point
Q
tPLH
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Timing Characteristics
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
Setup time is the minimum
time for the data to be present
before the clock.
D
CLK
Set-up time, ts
Hold time is the minimum time
for the data to remain after the
clock.
D
CLK
Hold time, tH
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Flip-flop Timing Characteristics
Other timing specifications include maximum clock
frequency and minimum pulse widths for various inputs.
Consult the following datasheet to compare propagation
delays, set-up time, hold time, and maximum clock
frequency for a 7474, a 74LS74, and a 74S74:
•7474 datasheet
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Output
lines
Q0
Flip-flop Applications
D
Principal flip-flop applications are for
temporary data storage, as frequency
dividers, and in counters (which are
covered in detail in Chapter 12).
C
R
Q1
D
C
R
Typically, for data storage applications,
a group of flip-flops are connected to
parallel data lines and clocked together.
We call such a group of flip-flops a
register. Data is stored until the next
clock pulse.
Q2
D
C
Parallel data
input lines
R
Q3
D
Clock
C
R
Clear
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Flip-flop Applications
For frequency division, it is simple to use a flip-flop in
the toggle mode or to chain a series of toggle flip flops to
HIGH
HIGH
continue to divide by two.
One flip-flop will divide fin
by 2, two flip-flops will
divide fin by 4 (and so on).
A side benefit of frequency
division is that the output
has an exact 50% duty
cycle.
QA
J
fin
CLK
K
QB
J
fout
CLK
K
fin
Waveforms:
fout
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