D-Type Flip Flops Benchmark Companies Inc PO Box 473768 Aurora CO 80047 Lecture Overview D Flip-Flops Asynchronous Input Sample Flip-Flop Applications
Download ReportTranscript D-Type Flip Flops Benchmark Companies Inc PO Box 473768 Aurora CO 80047 Lecture Overview D Flip-Flops Asynchronous Input Sample Flip-Flop Applications
Slide 1
D-Type Flip Flops
Benchmark Companies Inc
PO Box 473768
Aurora CO 80047
Slide 2
Lecture Overview
D Flip-Flops
Asynchronous Input
Sample Flip-Flop Applications
Slide 3
Gated D-Type Latch
The D-Latch is an expanded version of an RS Flip Flop.
The symbol shown is used to represent this type of flipflop.
Slide 4
Gated D-Type Latch
It is also known as transparent latch, data latch, or
simply a gated latch
Slide 5
Gated D-Type Latch
It has a data input and an enable signal (sometimes
named clock or control).
Slide 6
D-Type Flip-Flops
The D flip-flop can be interpreted as a primitive delay
line or zero-order hold, since the data is posted at the
output one clock cycle after it arrives at the input
Slide 7
D Flip-Flop
The Data Table below illustrates the output Q(n+1) with
respect to the Data (D) clocked (CLK) into the latch.
D
Q
Q
D CLK
Q
0
0
1
1
n+1
Slide 8
D Flip-Flop
As illustrated below the clock pulse into the Flip Flop (FF)
will synchronize the output.
D
Q
Q
CLK
D
Q
D CLK
Q
0
0
1
1
n+1
Slide 9
Application of D Flip-Flops
Data Storage
Counters & State Machine Designs
Logic Synchronizing
Divide By Circuits
Slide 10
Logic Synchronizing
Synchronizing data is done by clocking all D-Type FF with
the same clock. This puts data on A,B and C at the same
time.
Slide 11
Divide By Circuit using a D Flip-Flop
The D-Type FF can be configured to divide the pulse in half
by configuring the circuit below.
SIG_IN
SIG_OUT
Slide 12
Types of D Flip-Flops
D
Q
Q
D
Positive Edge Triggered
Q
Q
Negative Edge Triggered
The trigger happens during the designed trigger edge.
Slide 13
Types of D Flip-Flops
D
Q
Q
D
Q
Q
Positive Level Triggered
Negative Level Triggered
The trigger happens during the designed trigger level
Slide 14
Types of D Flip-Flops
Asynchronous Inputs
P-SET
D
Q
Q
CLR
D Flip-Flop w/ Preset & Clear
P-SET CLR D CLK
0
1 X X
1
0 X X
0
0 X X
1
1 0
1
1
1
Q
1
0
?
0
n+1
(preset)
(clear)
(illegal)
1
The FF can be designed with Preset (P-SET) or clear (CLR)
Slide 15
End of Lesson
D-Type Flip Flops
Benchmark Companies Inc
PO Box 473768
Aurora CO 80047
Slide 2
Lecture Overview
D Flip-Flops
Asynchronous Input
Sample Flip-Flop Applications
Slide 3
Gated D-Type Latch
The D-Latch is an expanded version of an RS Flip Flop.
The symbol shown is used to represent this type of flipflop.
Slide 4
Gated D-Type Latch
It is also known as transparent latch, data latch, or
simply a gated latch
Slide 5
Gated D-Type Latch
It has a data input and an enable signal (sometimes
named clock or control).
Slide 6
D-Type Flip-Flops
The D flip-flop can be interpreted as a primitive delay
line or zero-order hold, since the data is posted at the
output one clock cycle after it arrives at the input
Slide 7
D Flip-Flop
The Data Table below illustrates the output Q(n+1) with
respect to the Data (D) clocked (CLK) into the latch.
D
Q
Q
D CLK
Q
0
0
1
1
n+1
Slide 8
D Flip-Flop
As illustrated below the clock pulse into the Flip Flop (FF)
will synchronize the output.
D
Q
Q
CLK
D
Q
D CLK
Q
0
0
1
1
n+1
Slide 9
Application of D Flip-Flops
Data Storage
Counters & State Machine Designs
Logic Synchronizing
Divide By Circuits
Slide 10
Logic Synchronizing
Synchronizing data is done by clocking all D-Type FF with
the same clock. This puts data on A,B and C at the same
time.
Slide 11
Divide By Circuit using a D Flip-Flop
The D-Type FF can be configured to divide the pulse in half
by configuring the circuit below.
SIG_IN
SIG_OUT
Slide 12
Types of D Flip-Flops
D
Q
Q
D
Positive Edge Triggered
Q
Q
Negative Edge Triggered
The trigger happens during the designed trigger edge.
Slide 13
Types of D Flip-Flops
D
Q
Q
D
Q
Q
Positive Level Triggered
Negative Level Triggered
The trigger happens during the designed trigger level
Slide 14
Types of D Flip-Flops
Asynchronous Inputs
P-SET
D
Q
Q
CLR
D Flip-Flop w/ Preset & Clear
P-SET CLR D CLK
0
1 X X
1
0 X X
0
0 X X
1
1 0
1
1
1
Q
1
0
?
0
n+1
(preset)
(clear)
(illegal)
1
The FF can be designed with Preset (P-SET) or clear (CLR)
Slide 15
End of Lesson