Transcript 08.1 Latches. Flip-flops. RS latch.pptx

Latches. Flip-Flops.






Remember the state. Bistable elements.
RS NOR latch
RS NAND latch
Clocked RS NAND latch
RS Flip-Flop
JK Flip-Flop
P&H Appendix-B
Wakerly Ch.7
Remember the state
• The output of combinational logic is fully defined by
the current state of the inputs.
• How the circuit can hold (remember) the signal ?
• First Define the requirements for circuit:
• It should have a state:
• The state could be either 0 or 1.
• Current state
• Next state
• Should be possibility to see or to use that state
• Should be way to setup or to change the state
RS latch – bistable element
Define the behavior
1. If the S is active and R is passive then the latch is setup to 1.
2. If the R is active and S is passive then the latch is setup to 0.
3. If both S and R are passive then the latch keeps the state (holds the state).
Latch’s state on the output
Current
state (0,1)
S
Change state to 1
R
Change state to 0
Latch
Q
Next state (0,1)
Qn
Input signals can change the current
Q state to the next Qn state
RS-latch - creation
1. The truth table of RS latch.
Input variables
Function
S
R
Q
Qn
0
0
0
0
Hold
0
0
1
1
0
1
0
0
Reset
0
1
1
0
1
0
0
1
Set
1
0
1
1
1
1
0
X
Not
1
1
1
X
Allowed
2. Karnaugh map of RS latch for Qn function
and for input S, R, Q variables
S’
Q’
Q
1
R’
RRR
SSS
0
0010
00
010
Q=0,1
Q=0
Q=1
110
&
X
X
R
__
3.
Hold state
Set
Reset
S
Q=0,1
R QQ=0
Q=1
Qn = S + RQ
111
Q=0,1
Q=0
Q=1
1
1
R’
Simplified RS latch – RS NOR latch
Qn = S + R’Q = S + R’Q = S + R+Q’
We need 2 input NOR elements for this.
Q
Hold state
1
R
0
S
0
R+ Q’
Q=0,1
1
Q’=1,0
This is one of the simplest RS latches we can create. Usually it’s represented as a pair of gates
and this is called Basic RS NOR latch.
R
1
1
S
Q
Q’
RS NOR latch analyze
S
0
0
1
1
R
0
1
0
1
Q
Q
Q
Q
Q
Qn
Q
0
1
X
This diagram shows how really has to be used the RS NOR latch. All the time we have to keep
the R and S inputs in logical “0” level. If we want to set or reset the latch then we have to give to
the appropriate input for a short time the logical “1”.
1
0
1
0
1
R
S
S
R
Q
AQ
A
R and S work by signal “level”
or by top of the signal
1
Undefined
1
1
0
0
0
Retains
1
Undefined
RS NOR latch pros and cons
• Forbidden to have both inputs at a logic 1 level at the
same time
• Input signals actively drive their respective outputs to a
logic 0, rather than to a logic 1.
• the S input signal is applied to the gate that produces the Q'
output
• while the R input signal is applied to the gate that produces the
Q output.
• This reversal of inputs can be confusing
• The state is changed by the input signals level
RS NAND latch
_
_
_ _
Qn = S + R Q = S + RQ = S • RQ
Hold state
S
0
We call this Basic
NAND RS latch
S
1
Q=0,1
&
Q=1,0
&
R
0
Inverters are not being used due to
redundancy
R
1
RQ
RS NAND latch analyze
The truth table of RS latch.
S’
R’
Q
Qn
0
0
0
X
0
0
1
X
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
RS NAND latch sign.
RS NAND latch compact truth table.
S’
R’
Q
Qn
0
0
Q
X
0
1
Q
1
1
0
Q
0
1
1
Q
Q
__
S
Q
_
_
R
Q
Q – Previous state
Qn – Next state
RS NAND latch timing diagram
S’
R’
Q
Qn
0
0
1
1
0
1
0
1
Q
Q
Q
Q
X
1
0
Q
S’
0
0
1
1
0
R’
0
1
0
1
0
Undefined
1
0
Q
A
A
Retains
Undefined
RS basic NAND latch cons and pros
• Forbidden to have both inputs at a logic 0 level at
the same time
• The problem with the basic RS NAND latch is that
the active input levels are Zeroes.
• We need extra invertors to make the active levels to
Ones.
• The state is changed by the input signals level
The Clocked (gated) RS NAND latch
• normal rather than inverted inputs
• and a third input common to both gates which we can use
to synchronize his circuit with others of its kind.
CLK
0
1
1
1
S
R
S
Q
_
R
Q
CLK
Q
Nothing
happens
S
X
0
1
1
R
X
1
0
1
Q
Q
Q
Q
Q
Qn
Q
0
1
X
Clocked RS NAND latch drawbacks
• If both inputs are logic 1 when the clock is also logic 1,
the latching action is bypassed and both outputs will
go to logic 1.
• A major problem remaining is that this latch circuit
could easily experience a change in S and R input
levels while the CLK input is still at a logic 1 level.
• This allows the circuit to change state many times before
the CLK input returns to logic 0.