Transcript Flipflops - GTU PG School
A B f C Gates are combined into circuits by using the output of one gate as the input for another.
So, in these circuits the output depends only on the combination of the inputs.
Digital Circuits can also be as memory units.
So, in these circuits the output depends on the past state of the inputs and outputs.
These type of circuits are called as
sequential circuits
.
Output depends only on inputs.
Doesn’t possess any memory elements.
There will be no feedback from the output to input. easier to design & faster in operation.
Eg: MUX, DEMUX, ADDERS, ENCODERS & DECODERS Output depends on both input and past state outputs.
Possess memory elements.
Involves some kind of feedback.
lots of complexity involves in the design and slower in operation.
Eg : Flipflops, latches, registers, counters etc..
A Y = Ᾱ Ǫ Ǭ
At the time of power ON condition, Let us assume the node Q is logic 1
A
0 1
Y = Ᾱ
1 0
Ǫ Ǭ
This indicates that the cascade connection of 2 inverters with a feedback is capable of retaining the past information (i.e., capable of storing the past information).
And hence it can be considered as a memory element.
But, there is no input port and hence we don’t have the control over the data to be stored.
Q
n
0 1
Q
n+1
0 1
If A = 0, then Y = B’.
This states that if one of the input to NOR gate is grounded, then that NOR gate will act as a NOT gate.
A
0
B
0 0 1 1 0 1 1
Y
1 0 0 0
Ǫ Ǭ
Ǫ Ǭ
Ǫ Ǭ
But, even with modification, there is no input port and hence we don’t have the control over the data to be stored i.e., we don’t have the control over the output.
R S Ǫ Ǭ
If one of the input is Logic 0, the output will be complement of second input.
If one of the input is logic 1, then the output will be logic 0 irrespective of the second input.
A
0
B
0 0 1 1 0 1 1
Y
1 0 0 0
R
0
S
1 1
Ǫ
R
0
S
1
Ǫ
1
Ǭ
0
Ǭ
R
0
S
0
Ǭ Ǫ
R
0 0
S
1 0
Ǫ
1 1
Ǭ
0 0
R
1
S
0
Ǫ
1
Ǭ
R
0 0 1
S
1 0 0
Ǫ
1 1 0
Ǭ
0 0 1
R
0
S
0
Ǫ Ǭ
R
0 0 1 0
S
1 0 0 0
Ǫ
1 1 0 0
Ǭ
0 0 1 1
R S
Ǫ Ǭ 0 0 1 1
Ǫ Ǭ
R
0 0 1 0 1 0
S
1 0 0 0 1 0
Ǫ Ǭ
1 0 1 0 0 0 1 1 Invalid
R
Ǫ Ǭ
S
0 0 1 1 0 0 1 1 0 0 1 1
Ǫ Ǭ
0 0
R
0 0 1 0 1 0
S
1 0 0 0 1 0
Ǫ Ǭ
1 0 1 0 0 0 1 1 Invalid Race Though the input is stable, both 0 and 1 will race with each other at the output.
0 1 0 1 0
R S
0 1 0 0 0 1 0
Ǫ Ǭ
1 0 1 0 0 0 1 1 Invalid
Race State SET No Change RESET No Change INVALID RACE
S’ R’ Ǫ Ǭ
1 1 1 0 1
S’ R’
0 1 1 0 1 0 1
Ǫ Ǭ State
1 0 1 0 0 0 1 1 Invalid
SET No Change RESET No Change INVALID Race RACE
So, it can be concluded that a 2gate NAND latch can be considered as an ACTIVE LOW latch.
1 1 1 0 1
S’ R’
0 1 1 0 1 0 1
Ǫ Ǭ State
1 0 1 0 0 0 1 1 Invalid
SET No Change RESET No Change INVALID Race RACE
S’ R’ C
0 1 1 1 1
S
X 0 0 1 1
R
X 0 1 0 1
S’
1 1 1 0 0
R’
1 1 0 1 0 -
Ǫ
0 1 1 -
Ǭ
1 0 1
State No Change No Change RESET SET Invalid
Q n
0 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1
C
0 0 1 1 0 0 1 1 1 1 x x
S
0 0 1 1 0 0 1 1
R
x x 0 0 0 0 x x 1 1
Ǫ n+1
0 1 0 1
State No Change No Change No Change No Change RESET RESET SET SET Invalid Invalid
1 0 1 0 1 0
Q n
0 1 0 0 1 1 1 1 0 0
S
1 1 0 0 1 1 0 0
R Ǫ n+1
0 1 0 0 x x 1 1
0
4
1
5
3
7
2
6 Characteristic Equation
0 0, 0 1
0
1 0
1
0 0, 1 0 0 1
Latch is a memory element which is capable of storing one bit (either 0 or 1).
A Latch contains two output lines which are always complement to ach other.
A NOR latch is an ACTIVE HIGH latch.
A NAND latch is an ACTIVE LOW latch.
In order to enable or disable any latch to accept the input data, control signal line can be used to convert latches into controlled latches.
A controlled NAND latch is active high latch.
Generally, invalid state or RACE condition occurs in latches for certain pattern of inputs which are undesired and must be eliminated.
To eliminate the invalid and race conditions (occurs when the inputs are either ‘00’ and ‘11’), both the inputs must of RS latch must be compliment to each other.
Similar to behavior of controlled RS latch since…………..?????
C
0 1 1
D
X 0 1
S
X 0 1
R
X 1 0
Ǫ
0 1
Ǭ
1 0
State No Change Reset Set
Characteristic Equation
Why are the input terminals named as J,K??
0 1 1 0 (0) 1 (0) 0
C
0 1 1 1 1
J
X 0 0
K
X 0 1
S’
1 1 (1) (1)
R’
1 1 -
Ǫ
0 -
Ǭ
1
State No Change No Change RESET
1 0 1 0 (1) 1 (1) 1
C
0 1 1 1 1
J
X 0 0 1
K
X 0 1 0
S’
1 1 (0) (0)
R’
1 1 -
Ǫ
0 1 -
Ǭ
1 0
State No Change No Change RESET SET
1 1 1 0 (1) 1 (0)
C
0 1 1 1 1
J
X 0 0 1 1
K
X 0 1 0 1
S’
1 1 (0) (1)
R’
1 1 -
Ǫ
0 1 -
Ǭ
1 0
State No Change No Change RESET SET Toggle
Q n
0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1
C
0 0 1 1 0 0 1 1 1 1 x x
J
0 0 1 1 0 0 1 1
K
x x 0 0 0 0 1 1 1 0
Ǫ n+1
0 1 0 1
State No Change No Change No Change No Change RESET RESET SET SET Toggle Toggle
1 0 1 0 1 0
Q n
0 1 0 0 1 1 1 1 0 0
J
1 1 0 0 1 1 0 0
K Ǫ n+1
0 1 0 0 1 1 1 0
0
4
1
5
3
7
2
6 Characteristic Equation
0 0, 0 1
0
1 0, 1 1 0 1, 1 1
1
0 0, 1 0
Similar to behavior of controlled JK latch since…………..?????
C
0 1 1
T
X 0 1
J
X 0 1
K
X 0 1
Ǫ
-
Ǭ
-
State No Change No Change Toggle
Characteristic Equation
If the response time (time required for the output to respond for a corresponding change in input) of any latch is assumed be
1nS.
Then, it can be concluded that, for a T latch, the output toggles for 10 times if toggle state input (T=1) is in high state for 10nS.
For RS latch, RACE condition occurs for 10 times if the corresponding inputs (R=S=1) are high for 10nS.
These rapid changes in the output are undesirable and must be avoided.
So, these hazards can be eliminated by enabling the latch only once in a complete cycle.
Master – Slave Configuration of JK Latches
In a complete Cycle (which is spread over a period of 20nS, The flip-flop responds only once i.e., only during the falling edge.
This makes it possible to eliminate the race around condition in latches.
So, these hazards can be eliminated by enabling the latch only once in a complete cycle.
So, it would be better to make the memory elements edge sensitive instead of level sensitive.
Because, edges will occur only once in a cycle.
Edge sensitive memory elements are called flip-flops .
Latches are level sensitive and flip-flops are edge sensitive.
Latches will respond many no. of times in a single clk cycle.
But, flipflops will respond only once in a cycle.