Transcript EENG 2710 Ch 6

EENG 2710 Chapter 6
Introduction to Sequential Logic
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Chapter 6 Homework
Work on your project
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Sequential Circuit
• A digital circuit whose output depends not
only on the present combination of input,
but also on the history of the circuit.
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Sequential Circuit Elements
• Two basic types:
– Latch
– Flip-flop
• The difference is the condition under
which the stored bit changes.
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SR Latch
• The LATCH is a sequential circuit with two
inputs (SET and RESET).
• SET – an input that makes the device store a
logic 1.
• RESET – an input that makes the device store a
logic 0.
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SR Latch
• Two complementary outputs (Q , Q ).
• Outputs are always in opposite logic
states.
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Active HIGH or LOW Inputs
• Latches can have either active HIGH or
active LOW inputs.
• The output of the LATCH, regardless of
the input active level, is still defined as:
SET :
Q  1, Q  0
RESET : Q  0, Q  1
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Active HIGH or LOW Inputs
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NAND Latch Function Table
Qt 1
Qt  1
0 0
1
1
Function
Forbidden
0 1
1
0
SET
1 0
0
1
RESET
1 1
Qt
Qt
S
R
No Change
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NAND Latch Reset to Set Transition
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NAND Latch Reset to Set Transition
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NAND Latch Set to Reset Transition
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NAND Latch Reset to Set Transition
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NOR Latch Function Table
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NOR Latch Reset to Set Transition
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NOR Latch Reset to Set Transition
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NOR Latch Set to Reset Transition
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NOR Latch Set to Reset Transition
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Switch Bounce
• The condition where the closure of a
switch contact results in a mechanical
bounce before the final contact is made.
• In logic circuits, switch bounce causes
several pulses when a switch is closed.
– Can cause circuit to behave unpredictably.
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Switch Bounce
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Switch Debounce Circuit
S  1, R  1
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Gated SR Latch
• The time when a latch is allowed to change state is regulated.
• Change of state is regulated by a control signal called ENABLE.
• Circuit is a NAND latch controlled by steering gates.
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Latch ENABLE Input
EN
S
R
Qt+1
1
0
0
Qt
1
1
1
0
0
1
1
X
1
0
1
X
0
1
1
Qt
Function
No change
1
0
1
Reset
Set
Forbidden
Inhibited
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Gated D or Transparent Latch
• A latch whose output follows its data input when its
ENABLE input is active.
• When ENABLE is inactive, the latch stores the data
that was present when ENABLE was last active.
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Gated D Latch Function Table
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Flip-Flop Definition
• A gated latch with a clock input.
• The sequential circuit output changes when its CLOCK
input detects an edge.
• Edge-sensitive instead of level-sensitive.
• Positive edge: The transition from logic ‘0’ to logic ‘1’
• Negative edge: The transition from logic ‘1’ to logic ‘0’
• Symbol is a triangle on the CLK (clock) input of a flipflop.
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Positive Edge-Triggered D Flip-Flop
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Edge Detector
• A circuit that converts that active-edge of a CLOCK input
into a brief active-level pulse.
• Created using gate propagation delays.
• Can be positive or negative edge.
• The inverter in a below has 3 to 10ns propagation delay
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Operation of Positive Edge D Flip-flop
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VHDL – D Latch
d_latch_vhdl.vhd
-- D latch with active-HIGH level-sensitive enable
ENTITY d_latch_vhdl IS
PORT(
d, ena
: IN BIT;
q
: OUT BIT);
END d_latch_vhdl;
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VHDL – D Latch
ARCHITECTURE a OF d_latch_vhdl IS
BEGIN
PROCESS ( d, ena)
BEGIN
IF ( ena = ‘1’) THEN
q <= d;
END IF;
END PROCESS;
END a;
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JK Flip-Flop
• Two inputs with no illegal input states.
• With J and K both HIGH, the flip-flop toggles between
opposite logic states with each applied clock pulse.
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Negative Edge-Triggered JK Flip-Flop
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Toggle Action
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Toggle Applications
• Used to divide an input frequency in half.
• By cascading toggling flip-flops, a counter is created.
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Synchronous And
Asynchronous Circuits
• Synchronous circuits have sequential
elements whose outputs change at the
same time.
• Asynchronous circuits have sequential
elements whose outputs change at
different times.
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Synchronous and
Asynchronous Inputs
• Synchronous inputs of a flip-flop only
affect the output on the active clock
edge.
• Asynchronous inputs of a flip-flop
change the output immediately.
• Asynchronous inputs override
synchronous inputs.
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3-Bit Synchronous Circuits
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Flip-Flop Asynchronous Inputs
• Preset:
– An asynchronous set function, usually
designated as PRE
• Clear:
– An asynchronous reset function, usually
designated as CLR
• Both Preset and Clear usually have LOW
input active levels.
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Flip-Flop Asynchronous Inputs
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3-Bit Synchronous Circuits With
Asynchronous Reset
• An asynchronous input used to set a sequential circuit to a known
initial state.
• Usually a RESET tied to the CLR inputs of all flip-flops.
• When activated, the output of the sequential circuit goes LOW.
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Disadvantages of
Asynchronous Circuits
• Difficult to analyze operations.
• Intermediate states that are not part of
the desired design may be generated.
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JK Flip-Flop Asynchronous Inputs Function Table
CLR
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Unused Preset and Clear Inputs
• Disable by connecting to a logic HIGH (for
active-LOW inputs).
• In Quartus II the asynchronous inputs of
all flip-flop primitives are set to a default
level of HIGH.
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T (Toggle) Flip-Flop
• Output toggles on each applied clock
pulse when a synchronous input is active.
• Synchronous input is designated as ‘T’.
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T Flip-Flop Function Table
CLK
T
Qt+1
Function
↑
0
Qt
No change
↑
1
Qt
Toggle
0
X
Qt
Inhibited
1
X
Qt
Inhibited
↓
X
Qt
Inhibited
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D Flip-Flop Configured for Toggle Function
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