Transcript CHAPTER FIVE SYNCHRONOUS SEQUENTIAL LOGIC    It consists of a combinational circuit to which storage elements are connected to form a feedback path. The storage elements.

CHAPTER FIVE
SYNCHRONOUS SEQUENTIAL
LOGIC
1



It consists of a combinational circuit to which
storage elements are connected to form a
feedback path.
The storage elements are devices capable of
storing binary information.
The binary information stored in these
elements at any given time defines the state of
the sequential circuit at that time.
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SEQUENTIAL CIRCUITS
Inputs

Combinational
Circuit
Outputs
Memory
Elements
Synchronous
Inputs
Outputs
Combinational
Circuit
Flip-flops
Clock
3


The outputs in a sequential circuit are a function
not only of the external inputs, but also of the
present state of the storage elements.
The next state of the storage elements is also a
function of external inputs and the present state.
The behavior of an asynchronous sequential
circuit depends upon the input signals at any
instant of time and the order in which the inputs
change.
A
synchronous sequential circuit (clocked
sequential circuit) is a system whose behavior can
be defined from the knowledge of its signals at
discrete instants of time.

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


Synchronization is achieved by a timing device
called a clock generator, which provides a clock
signal having the form of a periodic train of clock
pulses .
The clock signal is commonly denoted by the clk.
The clock pulses determine when computational
activity will occur within the circuit, and other
signals (external inputs) determine what changes
will take place affecting the storage elements and
the outputs.
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
Storage elements that operate with signal levels
(rather than signal transitions) are referred to as
latches.

Those controlled by a clock transition are flip-flops.

Latches are said to be level sensitive devices.

Flip-flops are edge-sensitive devices.
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LATCHES

SR Latch (cross coupled NOR)
S R Q0
0 0 0
R 0
S
0
Q
0
Q’
1
Q = Q0
Q
Q
0
1
Initial Value
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LATCHES

SR Latch
S R Q0
0 0 0
0 0 1
R 0
S
1
Q
0
1
Q’
1
0
Q = Q0
Q = Q0
Q
Q
0
0
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LATCHES

SR Latch
R 1
S
0
S
0
0
0
R
0
0
1
Q0
0
1
0
Q
0
1
0
Q’
1
0
1
Q = Q0
Q=0
Q
Q
0
1
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LATCHES

SR Latch
R 1
S
1
Q
S
0
0
0
0
R
0
0
1
1
Q0
0
1
0
1
Q
0
1
0
0
Q’
1
0
1
1
Q = Q0
Q=0
Q=0
Q
0
0
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LATCHES

SR Latch
R 0
S
0
Q
S
0
0
0
0
1
R
0
0
1
1
0
Q0
0
1
0
1
0
Q
0
1
0
0
1
Q’
1
0
1
1
0
Q = Q0
Q=0
Q=1
Q
1
1
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LATCHES

SR Latch
R 0
S
1
Q
S
0
0
0
0
1
1
R
0
0
1
1
0
0
Q0
0
1
0
1
0
1
Q
0
1
0
0
1
1
Q’
1
0
1
1
0
0
Q = Q0
Q=0
Q=1
Q=1
Q
1
0
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LATCHES

SR Latch
R 1
S
0
Q
S
0
0
0
0
1
1
1
R
0
0
1
1
0
0
1
Q0
0
1
0
1
0
1
0
Q
0
1
0
0
1
1
0
Q’
1
0
1
1
0
0
0
Q = Q0
Q=0
Q=1
Q = Q’
Q
1
10
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LATCHES

SR Latch
R 1
S
10
Q
Q
1
0
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
Q
0
1
0
0
1
1
0
0
Q’
1
0
1
1
0
0
0
0
Q = Q0
Q=0
Q=1
Q = Q’
Q = Q’
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LATCHES

SR Latch
R
S
Q
Q
S
Q
R
Q
S R
Q
Q0
0
0
1
1
No change
0
Reset
1
0
Set
0
1
1 Q = Q’=0 Invalid
S
0
0
1
1
Q
R
0 Q = Q’=1 Invalid
Set
1
1
Reset
0
0
Q0
No change
1
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CONTROLLED LATCHES

SR Latch with Control Input (operates with signal level)
S
S
Q
C
R
Q
R
En S R
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Q
Q0
Q0
No change
No change
Reset
0
Set
1
Q = Q’ Invalid
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CONTROLLED LATCHES

D Latch (Transparent Latch)
C
S
D
Timing Diagram
Q
D
C
R
Q
Q
t
C=En D (data)
0
1
1
x
0
1
Q
Q0
0
1
No change
Reset
Set
Output may
change
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CONTROLLED LATCHES

D Latch (D = Data)
Timing Diagram
C
S
D
Q
D
C
R
C D
0 x
1 0
1 1
Q
Q
Q0
0
1
No change
Reset
Set
Q
Output may
change
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20
FLIP-FLOPS
When latches are used for the storage elements, a
serious difficulty arises. The state transitions of the
latches start as soon as the clock pulse changes to
the logic-1 level.
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


If the inputs applied to the latches change while
the clock pulse is still at the logic-1 level, the
latches will respond to new values and a new
output state may occur.
The new state of a latch appears at the output
while the pulse is still active. This output is
connected to the inputs of the latches through the
combinational circuit.
The result is an unpredictable situation, since the
state of the latches may keep changing for as long
as the clock pulse stays at the active level.
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
Controlled latches are level-triggered
C


Flip-Flops are edge-triggered
CLK
Positive Edge
CLK
Negative Edge
It operates with signal transitions
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FLIP-FLOPS

Master-Slave D Flip-Flop
D
D
C
D Latch
(Master)
Q
D
C
D Latch
(Slave)
Master
CLK
Q
Q
Slave
CLK
D
Looks like it is negative
edge-triggered
QMaster
QSlave
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FLIP-FLOPS

Edge-Triggered D Flip-Flop
D
Q
Q
Q(t+1) = D
Positive Edge
D
Q
Q
Negative Edge
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FLIP-FLOP CHARACTERISTIC EQUATIONS

Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
1 1
0 0
0 1
1 0
1 1
No change
Reset
Set
Toggle
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FLIP-FLOP CHARACTERISTIC EQUATIONS

Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
0 1
1 0
1 1
No change
Reset
Set
Toggle
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FLIP-FLOP CHARACTERISTIC EQUATIONS

Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
1
0 1
1
1 0
1 1
No change
Reset
Set
Toggle
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FLIP-FLOP CHARACTERISTIC EQUATIONS

Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
1
0 1
1
1 0
1
1 1
0
No change
Reset
Set
Toggle
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FLIP-FLOP CHARACTERISTIC EQUATIONS

Analysis / Derivation
J
Q
K
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
1
0 1
1
1 0
1
1 1
0
Q(t+1) = JQ’ + K’Q
K
0
J 1
1
1
0
0
0
1
Q
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FLIP-FLOPS

JK Flip-Flop
J
D
Q
Q
Q
Q
K
CLK
J
Q
D = JQ’ + K’Q
K
Q
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FLIP-FLOPS

T (toggle) Flip-Flop
T
J
Q
K
Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q
D
T
Q
Q
T
Q
Q
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FLIP-FLOP CHARACTERISTIC TABLES
D
Q
Q
J
Q
K
Q
T
Q
Q
D
0
1
J
0
0
1
1
T
0
1
Q(t+1)
0
1
Reset
Set
K Q(t+1)
0
Q(t)
1
0
0
1
1 Q’(t)
No change
Reset
Set
Toggle
Q(t+1)
Q(t)
Q’(t)
No change
Toggle
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FLIP-FLOPS WITH DIRECT INPUTS

Asynchronous Reset
D
Q
R
0
D CLK Q(t+1)
x
x
0
Q
R
Reset
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FLIP-FLOPS WITH DIRECT INPUTS

Asynchronous Reset
D
Q
Q
R
R
0
1
1
D CLK Q(t+1)
x
x
0
↑
0
0
↑
1
1
Reset
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