Transcript 11.2 Set-Reset Latch

Unit 11
Latches and Flip-Flops
Ku-Yaw Chang
[email protected]
Assistant Professor, Department of
Computer Science and Information Engineering
Da-Yeh University
Outline
11.1 Introduction
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
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Set-Reset Latch
Gated D Latch
Edge-Triggered D Flip-Flop
S-R Flip-Flop
J-K Flip-Flop
T Flip-Flop
Flip-Flops with Additional Inputs
Summary
Latches and Flip-flops
2
Introduction
Sequential switching circuits

The output depends on
Present input
Past sequence of inputs

‘remember’ something about the past history of the
inputs
Two commonly used memory devices in
sequential circuits


Latches – no clock input
Flip-flops
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Latches and Flip-flops
3
Feedback
The output of one of the gates is connected
back into the input of another gate in the circuit
so as to form a closed loop.
The rate at which the circuit oscillates is
determined by the propagation delay in the
inverter.
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Latches and Flip-flops
4
Two Inverters with
a Feedback Loop
Two stable conditions

Often referred to as stable states
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Latches and Flip-flops
5
Outline
11.1 Introduction
11.2 Set-Reset Latch
11.3
11.4
11.5
11.6
11.7
11.8
11.9
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Gated D Latch
Edge-Triggered D Flip-Flop
S-R Flip-Flop
J-K Flip-Flop
T Flip-Flop
Flip-Flops with Additional Inputs
Summary
Latches and Flip-flops
6
Set-Reset Latch
Introduce feedback into a NOR-gate circuit


S=R=0 is a stable condition
S=1 and R=0 is a stable condition
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Set-Reset Latch
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Latches and Flip-flops
8
Set-Reset Latch
This circuit is said to have memory because
its output depends not only on the present
inputs, but also on the past sequence of
inputs.
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9
Set-Reset Latch
R = S = 1 is not allowed


The outputs P and Q are always complements,
that is, P = Q’.
The circuit is in cross-coupled form.
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10
Set-Reset Latch
An input S = 1 sets the output to Q = 1
An input R = 1 resets the output to Q = 0
R and S cannot be 1 simultaneously
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11
Improper S-R Latch Operation
The latch may continue to oscillate if the gate
delays are equal.
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12
Timing Diagram
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13
S-R Latch Operation
S(t)
0
0
0
0
1
1
1
1
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R(t)
0
0
1
1
0
0
1
1
Q(t)
0
1
0
1
0
1
0
1
Latches and Flip-flops
Q(t+e)
0
1
0
0
1
1
14
Map and Equation of the Latch
Next-state equation, or characteristic equation

Q+ = S + R’ Q
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(SR=0)
Latches and Flip-flops
15
S-R Latch Applications
Components in more complex latches and flipflops
Debouncing switching
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S-R Latch
An alternative form of the S-R latch uses
NAND gates
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S-R Latch
S = 0 will set Q to 1
R = 0 will set Q to 0
S = R = 0 is not allowed
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S
1
1
1
1
0
0
0
0
Latches and Flip-flops
R
1
1
0
0
1
1
0
0
Q Q+
0 0
1 1
0 0
1 0
0 1
1 1
0 1 18