Transcript PowerPoint 프레젠테이션 - ETH TIK

Lecture 2. Sequential Logic Design
Principles
1
Sequential logic circuits

Outputs depend not only on its current inputs, but also on the
past sequence of inputs

The past sequence of inputs can be represented as states

The state

A collection of state variables whose values at any one time contain all the
information about the past necessary to account for the circuit’s future
behavior.
2
Clock signals

The state changes of most sequential circuits occur at times
specified by a free-running clock signal.
3
Bistable circuits

No inputs and two outputs, Q and Q_L


The output Q is a state
The values of the state : 0 and 1
[ 3 equilibrium points ]
4
Latch and flip-flop

A basic building blocks of most sequential circuits.

Flip-flop
 Sampling its inputs and changing its outputs only when a clock
signal is changing.

Latch
 Watching its inputs continuously and changing its output at any
time.
5
S-R (set-reset) latch
reset or clear
set or preset
metastable or
oscillation
(a) normal inputs (b) S and R asserted simultaneously
6
S-R (set-reset) latch

A basic rule of latch operation


The latch outputs should be complements
If S=R=1, then Q=QN=0

S-R latch violates the basic rule
1→ 0
0→ 1 → 0 → 1
Oscillation
1→ 0
0→ 1 → 0 → 1
7
S-R (set-reset) latch
pulse shorter than the
minimum pulse width
metastable
[ propagation delays ]
[ minimum pulse width ]
8
S-R (S-bar-R-bar) latch

In CMOS and TTL logic families, S-bar-R-bar latches are
used much more often than S-R latches because NAND gates
are preferred over NOR gates.
9
Why NAND gates are preferred in CMOS?
PMOS transistors are deployed in parallel in NAND gates.
PMOS:
slower,
higher impedance
NMOS:
faster,
higher impedance
10
S-R latch with enable
S=R=1 and C changes from 1 to 0
the next state is unpredictable and may become metastable
11
D latch

Simply to store bits of information
 Each bit is presented on a signal line, and we’d like to store it
somewhere.
12
D latch
setup- and hold-time window of C input
D changes during the setup- and hold-time window of C
the output of the latch is unpredictable, and may become metastable
13
Positive edge-triggered D flip-flop
master latch
slave latch
Dynamic-input
indicator
14
Positive edge-triggered D flip-flop
setup- and hold-time window of CLK
D inputs must not be change during the setup- and hold-time window
15
Setup and hold times for an edge-triggered
D flip-flop
tsu : the setup time
[ Roth ]
th : the hold time
t p : the propagation delay
Using these timing parameters, we can determine the minimum clock period
for a circuit which will not violate the timing constraints.
16
Negative edge-triggered D flip-flop
[ Positive –edge-triggered D flip-flop with preset and clear ]
asynchronous
input
asynchronous
input
17
Positive-edge-triggered D flip-flop with enable
[ Holding the last value stored + loading a new value ]
18
Scan flip-flop (for testing)
 TE
: test enable
 TI : test input
scan in
scan out
[ Scan chain with 4 flip-flops ]
19
S-R flip-flop
 S=R=0
 S=1, R=0
 S=0, R=1
 S=R=1
No state change
Set Q to 1 (after active Ck edge)
Reset Q to 0 (after active Ck edge)
Not allowed
20
J-K flip-flop
J
K
Q
Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
Q  JQ  K Q
unlike S-R flip-flop
b  Truth table and characteristic equation
21
T (toggle) flip-flop
[ Positive-edge-triggered T flip-flop ]
[ Positive-edge-triggered T flip-flop with enable ]
22
Clocked synchronous state-machine analysis

state machine = sequential circuits

clocked
 Flip-flops employ a clock input

synchronous
 All of the flip-flops use the same clock signal
 State-machine changes state only when a triggering edge (or
tick) occurs on the clock signal
23
State-machine structure
[ Mealy machine ]
a set of n flip-flops
Most state machines nowadays using PLDs, CPLDs, FPGAs, or ASICs
are designed with positive-edge triggered D flip-flops
24
State-machine structure
[ Moore machine ]
[ Mealy machine with pipelined outputs ]
25
Characteristic equations
[ Q* : a next state, Q : a present state ]
26
Characteristic equations
S t 
Rt 
Qt 
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
11
0
1
0
1
0
1
0
1
Qt   
0
1
0
0
1
1
-

Inputs not allowed
Q*  S  RQ
27
Analysis of state machines with D flip-flops



Next state = F(current state, input)
Output = G(current state, input)
The basic three steps for the analysis of a state machine
 Determining the next-state and output functions F and G
 Constructing a state/output table
 Drawing a state diagram
28
A state machine example with D flip-flops
Q0, Q1 : state
EN : input
MAX : output
29
Transition equations

excitation equations



since D flip-flops are used



Q0* = D0
Q1* = D1
transition equations



D0 = Q0•EN’ + Q0’•EN
D1 = Q1•EN’ + Q1’•Q0•EN + Q1•Q0’•EN
Q0* = Q0•EN’ + Q0’•EN
Q1* = Q1•EN’ + Q1’•Q0•EN + Q1•Q0’•EN
output equation

MAX = Q1•Q0•EN
30
State/output table
(a) transition table
(b) state table
(c) state/output table

Q0*, Q1* : next state
 S* : next state name
[ state name ]
A = 00 B = 01
C = 10 D = 11
31
State diagram (state graph)
This example is Mealy machine
circle (or node)
arrow (or directed arc)
When the input EN has became ‘1’ at the state C,
the output becomes ‘0’ and
the machine’s state will change into D for the following clock edge.
32
Moore machine Implementation
33
Timing Diagram
State transitions
Moore vs Mealy
34
Another example: Moore machine
Q0, Q1, Q2 : state
X, Y : input
Z1, Z2 : output
35
Another example: Moore machine
[ state/output table ]
36
Another example: Moore machine
37
Clocked synchronous state-machine design
1.
2.
3.
4.
5.
6.
7.
8.
9.
state/output table
state minimization
state assignment
transition/output table
excitation table
excitation equations
output equations
logic diagram
design
38
Design example


Design a clocked synchronous state machine with two inputs,
A and B, and a single output Z that is 1 if:

A had the same value at each of the two previous clock ticks,
or

B has been 1 since the last time that the first condition was
true
Otherwise, the output should be 0
39
Design example

Our example is a Moore machine

Its output depends only on the current state, that is, what
happened in previous clock periods.
40
Design example : state table construction

States





INIT : initial state
A0 : previous tick에서 입력 A가 0인 경우
A1 : previous tick에서 입력 A가 1인 경우
OK0 : two previous ticks에서 입력 A가 연속으로 0인 경우
OK1 : two previous ticks에서 입력 A가 연속으로 1인 경우
41
State minimization
[ Non-minimal state table ]

Identify equivalent states


OK00 and OKA0 are equivalent
OK11 and OKA1 are equivalent
42
State assignment
state assignment
= assigning binary combinations to states
= coded states
1-bit : 1 flip-flop
# of flip-flops needed to code m states = ┌ log2m ┐
43
State assignment

The state assignment often has a major effect on
circuit cost


It may interact with other factors, such as the choice of
storage element (e.g., D vs. J-K flip-flops) and the realization
approach for excitation and output logic (e.g., a sum of
products or a product of sums)
How do we choose the best state assignment?


The best solution is to try all the assignment. But that’s too
much work
Most digital engineers rely on experience and several
practical guidelines
44
Synthesis using D flip-flops
[ transition and output table
using decomposed assignment ]
[ transition and output table
using D flip-flops ]
45
Synthesis using D flip-flops
D 1 = Q1 + Q2’Q3’
[ Excitation map for D1 : 5-input Karnaugh map
assuming that unused states go to state 000
(don’t care is also possible) ]
46
Synthesis using D flip-flops
D2 = Q1Q3’A’ + Q1Q3A + Q1Q2B
D3 = Q1A + Q2’Q3’A
[ Excitation map for D2 and D3 ]
47
Synthesis using D flip-flops
Z = Q1Q2Q3’ + Q1Q2Q3
= Q1Q2
The output equation is simpler than the excitation equations,
because the output is a function of state only.
48
A String Recognizer Example

Design a string recognizer with one input (X) an
d one output (Z):

The output is asserted whenever the input sequence …01
0… has been observed, as long as the sequence 100 has
never been see.
X: 00101010010 …
Z: 00010101000 …
X: 11011010010 …
Z: 00000001000 …
49
A String Recognizer Example

State/output table
X
Meaning
Initialized
Got “0”
Got “1”
S
Sinit
S0
S1
0
S0
S0
S10
1
S1
S01
S1
Z
0
0
0
Got “01”
Got “10”
Got “010”
S01
S10
Sok
Sok
Sf
Sf
S1
S01
S01
0
0
1
Got “100”
S0
Sf
Sf
0
S*
50
A String Recognizer Example

State diagram
X=0
Sinit
Z=0
X=1
X=0
S0
Z=0
X=1
X=1
S01
Z=0
X=1
X=1
X=0
Sok
Z=1
X=1
S1
Z=0
X=0
S10
Z=0
X=0
X=0
1
Sf
Z=0
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Designing state machines using state diagrams

Most people like to take a graphical approach to
design


It is the basis of the method used by CAD tools


for that reason, state diagrams are often used to design smallto medium-sized state machines
it can synthesize logic from graphical or HDL-based state
diagrams
There is no ambiguity in a state table, but there may
exist ambiguity in a state diagram
52
Designing state machines using state diagrams
[ left turn ]
[ right turn ]
Input signals : LEFT, RIGHT, HAZ (emergency flasher)
53
Designing state machines using state diagrams
[ 8 states and 6 outputs ]
[ state diagram 1 ]
54
Designing state machines using state diagrams
Handling multiple inputs asserted simultaneously
It is unambiguous because
the transition expressions on the arcs
leaving each state are
mutually exclusive and all-inclusive
[ state diagram 2 ]
55
Designing state machines using state diagrams
[ state assignment :
8 states → 3 flip-flops ]
[ Enhanced state diagram ]
56
Designing state machines using state diagrams
*
*
*
*
[ transition list ]
57
State-machine synthesis using transition lists

A transition equation for a next-state variable V*
V*
=
∑
(transition product-term)
transition-list rows where V*=1

[Car light example] Transition equation for Q2*
Q2* = Q2' · Q1' · Q0' · (HAZ + LEFT · RIGHT)
+ Q2' · Q1' · Q0' · (RIGHT · HAZ' · LEFT')
+ Q2' · Q1' · Q0 · (HAZ)
+ Q2' · Q1 · Q0 · (HAZ)
+ Q2 · Q1' · Q0 · (HAZ')
+ Q2 · Q1' · Q0 · (HAZ)
+ Q2 · Q1 · Q0 · (HAZ')
+ Q2 · Q1 · Q0 · (HAZ)
58
State-machine synthesis using transition lists

Excitation equations



Variation on the scheme


If we use D flip-flops, then Q* = D
PLD and ASIC-based state-machine designs use D flip-flops
If fewer ‘0’ than ‘1’, V* = ∏ (transition sum-term)
Realizing the state machine (synthesis)

Use VHDL or Verilog program

Synthesize a PLD, FPGA or ASIC realization
59
The Guessing Game Example – first trial
Input: G1-G4, Output: L1-L4, ERR
LEDs (L1-L4) diplay a rotating 1-out-of-4 pattern.
When button being pressed, it stops rotating and displays
‘ERR” properly.
60
The Guessing Game Example - completed
Enhanced with two separate states SOK/SERR
61
Decomposing state machines

Large state machine


Difficult to conceptualize, design, debug
Solution: collection of smaller state machines

Partitioning into submachines
The most commonly used
submachine is a counter.
62
Hierarchical FSM
a
a
BC
A
A
B
b
c
B
b
C
b
b’c
C
Some states can be grouped into a big one to minimize the complexity.
It is important to prioritize the events (transition conditions).
63
Concurrent FSM
ac’
a
AC
A
b
C
c
bc’
B
a’c
D
AD
BC
ac
bc
a
b’c
BD
b
A FSM can be completed divided into several independent ones.
All combinations of the states (from several sub FSM) should be
considered.
64
More complicated guessing game
Complicated with randomized enable signal
65
Feedback sequential-circuit analysis

Analysis of feedback sequential-circuits is done by the notion of
fundamental-mode circuits.

Fundamental-mode circuits
 Inputs are not allowed to change simultaneously
 Feedback sequential circuits are the most common example
 Even though “almost simultaneous” input changes may occur
in practice, we assume that nothing happens simultaneously
 The impossibility of simultaneous events is supported by the
varying delays of circuit components
66
Feedback sequential-circuit analysis
Fictional buffer with 10ns delay
Y : current state
D and C : inputs
Y* : the next value of Y
Excitation equation for Y*
Y* = (C·D) + (C·D'+Y') '
67
Feedback sequential-circuit analysis
S0 = 0
S1 = 1
[ transition table ]

[ state table ]
Total state = internal state + input state
 Y : internal state
 C and D : input state
 S0/00 : stable total state
 S0/11 : unstable total state
68
Feedback sequential-circuit analysis

Output equations
 Q = C·D+C'·Y+D·Y
 QN = C·D'+Y'
69
Feedback sequential-circuit analysis
We change D to 1
We change C to 1
automatic change
to stable total
state S1/11
70
Feedback sequential-circuit analysis

Start in stable total state S1/11
 Suppose that C and D are both “simultaneously” set to 0
 In reality, the circuit behaves as if one or the other input went
to 0 first
 The final state of the circuit is unpredictable
When C changes first
When D changes first
71
Feedback sequential-circuit analysis
[ transition table ]
72
Race

A race is said to occur when multiple internal variables change
state as a result of a single input changing state.
Change CLK from 0 to 1
(single input change)
→ Next internal state is 000
(2-variables Y2 and Y3 change
from 011)
→ Race has occurred !!!
73
Noncritical race

Logic signals never really change “simultaneously”.
Two possible paths to
stable total state 000/10
(1) 011 → 001 → 000
(2) 011 → 010 → 000

The final state (000/10) does not depend on the order in which the
state variables change
 Noncritical race
74
Critical race
The circuit may end up in
internal state 000 or 001,
depending the order and speed of
the internal variable changes
→ Critical race
When you design a feedbackbased sequential circuit, you
must ensure that its transition
table does not contain any
critical races. Otherwise, the
circuit may operate
unpredictably.
75
State tables and flow tables
having no critical races
in state S0/11
input change to 01
→ S2/01 → S6/01
[ state/output table ]
[ transition table ]
cannot be reached from
a stable total state as
the result of a single
input change
[ flow/output table ]
eliminating multiple
hops and unused
internal states
(S1, S4, S5)
76
State tables and flow tables
[ flow/output table showing the positive-edge triggered D flip-flop’s behavior ]
S0/11 (Q=0) → CLK changes to 0
→ S0/01 → S6/01 (Q=0)
→ CLK changes to 1
→ S6/11 (Q=1) → S7/11 (Q=1)
when CLK 0 → 1, D input → Q
77
State tables and flow tables
State-minimization
5 states (3 flip-flops) → 4 states (2 flip-flops)
78
Feedback Sequential-Circuit Design

Some circuits can be designed easily


Q* = (forcing term) + (holding term) Q
The excitation logic in a feedback sequential circuit must be
hazard free.
79
Feedback Sequential-Circuit Design

In general, we start by constructing a primitive flow table


One stable state per row
Then, minimize the flow table
Example: 2 bit input P, R and 1 bit output Z
The output should be set to 1 whenever a 0-to-1 transition occurs on P (pulse),
and should be reset to 0 whenever R (reset) is 1.
80
Feedback Sequential-Circuit Design


Build a primitive flow table
Then, minimize.
81
Feedback Sequential-Circuit Design

Reduced flow table
82
Feedback Sequential-Circuit Design

Race-free state assignment
Adjacency graph
A flow table example
Race-free assignment
83
Sequential-circuit design with VHDL
event attribute
→ to describe edge-triggered
behavior
“CLK′event” is true for any
change on the signal CLK
84
VHDL clock generator
Generating a 100-MHz clock
with a 60% duty cycle
using loop
85
VHDL coding style

There are many possible coding styles for creating state machines in VHDL
86
VHDL design example


Design a clocked synchronous state machine with two inputs, A and B, and a
single output Z that is 1 if:

A had the same value at each of the two previous clock ticks, or

B has been 1 since the last time that the first condition was true
Otherwise, the output Z should be 0
87
VHDL design example
CLOCK signal이 0에서 1로 바
뀔 때 next state Snext를 이용해
current state Sreg 값을 새롭게
한다.
A, B, lastA, Sreg signal들 중 하
나가 바뀔 때, next state Snext
값을 새롭게 한다.
Current state Sreg signal 값에
따라 output Z를 계산한다.
88
VHDL test bench
 A test
bench specifies a sequence of
inputs to be applied by the simulator to
a VHDL design.
 A test bench is a separate VHDL
program.
The entity being tested called UUT
Creating a free-running clock
Use an assert statement to stop
the simulation and print the
message “Failed test 1” if Z is
not 0 at this point.
89