Slide 1

Unit 11
Latches and Flip-Flops
Ku-Yaw Chang
[email protected]
Assistant Professor, Department of
Computer Science and Information Engineering
Da-Yeh University


Slide 2

Outline
11.1 Introduction
11.2 Set-Reset Latch

11.3 Gated D Latch
11.4
11.5
11.6
11.7
11.8
11.9
2004/04/26

Edge-Triggered D Flip-Flop
S-R Flip-Flop
J-K Flip-Flop
T Flip-Flop
Flip-Flops with Additional Inputs
Summary
Latches and Flip-flops

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Slide 3

Gated D Latch
Two inputs



A data input (D)
A gate input (G)

Constructed from an S-R latch and gates

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Slide 4

Timing Diagram
G=1



The Q output follows the D input.
Transparent latch

G=0


The Q output holds the last value of D (no state
change)

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Latches and Flip-flops

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Slide 5

Symbol and Truth Table
G
0
0
0
0
1
1
1
1
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Latches and Flip-flops

D
0
0
1
1
0
0
1
1

Q
0
1
0
1
0
1
0
1

Q+
0
1
0
1
0
0
1
1
5


Slide 6

Outline
11.1 Introduction
11.2 Set-Reset Latch
11.3 Gated D Latch

11.4 Edge-Triggered D Flip-Flop
11.5
11.6
11.7
11.8
11.9
2004/04/26

S-R Flip-Flop
J-K Flip-Flop
T Flip-Flop
Flip-Flops with Additional Inputs
Summary
Latches and Flip-flops

6


Slide 7

D Flip-Flop
Two inputs


D (data)



Ck (clock)

The output changes only in response to the
clock, not to a change in D.

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Slide 8

D Flip-Flop
The output can change in response to a 0 to
1 transition on the clock input


Triggered on the rising edge (or positive edge)

The output can change in response to a 1 to
0 transition on the clock input


Triggered on the falling edge (or negative edge)

Active edge


The clock edge (rising or falling) that triggers the
flip-flop

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Slide 9

D Flip-Flop
The state after the active clock edge (Q+) is
equal to the input (D) before the active edge.


Characteristic equation : Q+ = D

D
0
0
1
1
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Q
0
1
0
1
Latches and Flip-flops

Q+
0
0
1
1
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Slide 10

D Flip-Flop
The output change are delayed


Falling edge trigger

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Slide 11

D Flip-Flop
A rising-edge-triggered D flip-flop



two gated D latches
an inverter

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Latches and Flip-flops

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Slide 12

D Flip-Flop Time Analysis

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Slide 13

Setup and Hold Times
Propagation delay is the time between



the active edge of the clock
the resulting change in the output

If D changes at the same time as the active
edge, the behavior is unpredictable.
Setup time (tsu)


the amount of time that D must be stable before the
active edge

Hold time (th)


the amount of time that D must hold the same value
after the active edge

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Slide 14

Setup and Hold Times
The times at which D is allowed to change
are shaded in the following timing diagram.

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Slide 15

Determination of
Minimum Clock Period

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