#### Transcript Chapter 5 Synchronous Sequential Logic

Synchronous Sequential Logic Chapter 5

Sequential Circuits • • • Combinational circuits + storage (store binary information) Binary information stored defines the state of the sequential circuit External input + present state determine the binary value of outputs and change state in storage elements

Sequential Circuits Block diagram of a sequential circuit

Sequential Circuits • • Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time Asynchronous sequential circuit is a system whose behavior depends on the input signals at any instant of time and the order in which the inputs change

Storage elements in synchronous sequential circuits • Latches: Operate on signal levels – Level-sensitive devices • Flip-Flops: Controlled by a clock transition – Edge-sensitive devices • Latches are the basic circuits from which all flip-flops are constructed

Sequential Circuits Synchronous clocked sequential circuit

Storage Elements: Latches What do you observe in this circuit?

Exercise: Group discussion.

Suppose that Q=1 and Q’=0. What happens with the circuit if S is set to 1 and R is set to 0? What happens if S and R are both set to 0?

What happens if S is set to 0 and R is set to 1?

What happens if S and R are both set to 0?

What happens if S and R are both set to 1?

Storage Elements: Latches Set state Reset state SR latch with NOR gates

Storage Elements: Latches Exercise: Group discussion.

Suppose that Q=1 and Q’=0. What happens with the circuit if S is set to 1 and R is set to 0? What happens if S and R are both set to 1?

What happens if S is set to 0 and R is set to 1?

What happens if S and R are both set to 1?

What happens if S and R are both set to 0?

Storage Elements: Latches Reset state Set state SR latch with NAND gates or R’S’ latch

Storage Elements: Latches Exercise: Group discussion.

Suppose that Q=1 and Q’=0. What happens with the circuit if S is set to 1, R is set to 0 and 𝐸𝑛 = 0 ?

What happens with the circuit if S is set to 1, R is set to 0 and 𝐸𝑛 = 1 ? What happens if S is set to 0, R is set to 1 and 𝐸𝑛 = 0 ?

What happens if S is set to 0, R is set to 1 and 𝐸𝑛 = 1 ?

What does 𝐸𝑛 do?

Storage Elements: Latches SR latch with control input

Storage Elements: Latches Compare these two latches. What advantage(s) could have one over the other?

D latch (transparent latch) D latch

Storage Elements: Latches Graphic symbols for latches

Trigger Storage Elements: Flip-Flops Latch Flip-Flop Compare the two types of trigger signals.

Clock response in Latch and Flip-Flop

Storage elements: Flip-Flops Master-slave D flip-flop Analyze the operation of this circuit. Assume initially Q=0, D=1, Clk=0. What happens when Clk changes to 1? What happens while Clk remains at 1? What happens when Clk changes to 0?

Other edge-triggered D flip-flop Discuss with your neighbor classmate the operation of this circuit. Assume some initial conditions.

D-type positive-edge-triggered flip-flop

Edge-triggered D flip-flop Graphic symbol for edge-triggered D flip-flop

Other flip-flops JK flip-flop Let 𝑄 𝑡 be the state of output 𝑄 output at time 𝑡 + 1 at time 𝑡 . Analyze what happens to the for all the different combinations of the 𝐽 and 𝐾 inputs. Use the table on the following slide.

Table for the analysis of 𝐽𝐾 flip-flop For the analysis of the 𝐽𝐾 flip-flop fill in the following table.

𝐽 0 0 1 1 𝐾 0 1 0 1 𝑄(𝑡 + 1) Input function to D flip-flip input: 𝐷 = 𝐽𝑄 ′ + 𝐾 ′ 𝐽

Other flip-flops T flip-flop (Toggle) Fill in the following table for the Toggle flip-flop 𝑇 0 1 𝑄(𝑡 + 1)

Characteristic tables

Direct inputs D flip-flop with asynchronous reset 1 1

Characteristic equations • • • • Describe logical properties of a flip-flop, just like a characteristic table, e.g.: For a D flip-flop: 𝑄 𝑡 + 1 = 𝐷 For a JK flip-flop: 𝑄 𝑡 + 1 = 𝐽𝑄 ′ + 𝐾 ′ 𝑄 , and For a T-flip-flop: 𝑄 𝑡 + 1 = 𝑇 ⊕ 𝑄 = 𝑇𝑄 ′ 𝑇 ′ 𝑄 +

Analysis of Clocked Sequential Circuits • • • • Describes what a circuit will do under certain operating conditions Behavior depends on inputs, outputs, and the state of flip-flops Outputs are function of inputs and present state Analysis obtains a table or diagram for the time sequence of inputs, outputs and internal states, and includes time sequence

State equations 𝐴 𝑡 + 1 = 𝐴 𝑡 𝑥 𝑡 + 𝐵 𝑡 𝑥(𝑡) 𝐵 𝑡 + 1 = 𝐴′ 𝑡 𝑥 𝑡 𝑦 𝑡 = [𝐴 𝑡 + 𝐵 𝑡 ]𝑥′ 𝑡 𝐴 𝑡 + 1 = 𝐴𝑥 + 𝐵𝑥 𝐵 𝑡 + 1 = 𝐴′𝑥 𝑦 = (𝐴 + 𝐵)𝑥′

State table

State table

State table • • Exercise: Compare tables 5.2 and 5.3. What makes the difference?

Compare any of the state tables (5.2 or 5.3) with the state equations. How do you relate equations and table? How do you obtain one from the other?

𝑥/𝑦 0/0 00 𝐴𝐵 State diagram 0/1 10 1/0 0/1 1/0 0/1 1/0 0 01 1 11 1/0 0 1

Flip-flops input equations or excitation equations 𝑥 𝑦 𝑄 𝐷 𝑄 = 𝑥 + 𝑦

Flip-flops input equations Input equations 𝐷 𝐴 = 𝐴𝑥 + 𝐵𝑦 𝐷 𝐵 = 𝐴′𝑥 Output equation 𝑦 = (𝐴 + 𝐵)𝑥′

Analysis of circuits with flip-flops State table has four sections: Present state Inputs Next state Outputs

Analysis of circuits with flip-flops • • • Determine the flip-flop input equations in terms of the present state and input variables List the binary values of each input equation Use the corresponding flip-flop characteristic table to determine the next-state values in the state table

Analysis with D flip-flops 𝐷 𝐴 = 𝐴 ⊕ 𝑥 ⊕ 𝑦 𝐴(𝑡 + 1) = 𝐴 ⊕ 𝑥 ⊕ 𝑦

Analysis with JK flip-flops Input equations 𝐽 𝐴 = 𝐵 𝐾 𝐴 = 𝐵𝑥′ 𝐽 𝐵 = 𝑥′ 𝐾 𝐵 = 𝐴 ⊕ 𝑥 = 𝐴 ′ 𝑥 + 𝐴𝑥′

Analysis with JK flip-flops 𝐴 𝑡 + 1 = 𝐽𝐴 ′ + 𝐾 ′ 𝐴 𝐵 𝑡 + 1 = 𝐽𝐵′ + 𝐾 ′ 𝐵 Substituting the values of 𝐽 𝐴 and 𝐾 𝐴 for 𝐴 , and 𝐽 𝐵 and 𝐾 𝐵 we obtain: 𝐴 𝑡 + 1 = 𝐵𝐴 ′ + 𝐵𝑥 ′ ′ 𝐴 = 𝐴 ′ 𝐵 + 𝐴𝐵 ′ + 𝐴𝑥 𝐵 𝑡 + 1 = 𝑥 ′ 𝐵 ′ + 𝐴 ⊕ 𝑥 ′ 𝐵 = 𝐵 ′ 𝑥 ′ + 𝐴𝐵𝑥 + 𝐴 ′ 𝐵𝑥′

Analysis with JK flip-flops

Analysis with JK flip-flops

Analysis with T flip-flops

Analysis with T flip-flops Characteristic equation of T flip-flop 𝑄 𝑡 + 1 = 𝑇 ⊕ 𝑄 = 𝑇 ′ 𝑄 + 𝑇𝑄′ Input Equations 𝑇 𝐴 = 𝐵𝑥 𝑇 𝐵 = 𝑥 Output Equations 𝑦 = 𝐴𝐵 State Equations 𝐴 𝑡 + 1 = 𝐵𝑥 ′ 𝐴 + 𝐵𝑥 𝐴 ′ = 𝐴𝐵 ′ + 𝐴𝑥 ′ + 𝐴 ′ 𝐵𝑥 𝐵(𝑡 + 1) = 𝑥⨁𝐵

Analysis with T flip-flops

Mealy and Moore models of finite state machines

State Reduction and Assignment • • • • • Analysis of sequential circuit starts with circuit and finishes with state table or diagram Design starts with state table or diagram State reduction aims at exhibiting the same input-output behavior but with a lower number of internal states Fewer internal states leads to fewer flip-flops May lead to use more gates

State reduction An infinite number of input sequences can be applied to a circuit, for example, the one whose state diagram is shown

*State*

Input Output

*a*

0 0

*a*

1 0

*b*

0 0

*c*

1 0

*d*

0 0

Algorithm for state reduction • • Two states are said to be equivalent if: – For each member of the set of inputs they give exactly the same output and send the circuit to either • The same state or • An equivalent state When two states are equivalent, one of them can be removed

State reduction Change *g *by *e*, which is the equivalent state Exercise: go through Table 5.6 and try to find equivalent states applying the algorithm described before.

State reduction

State reduction

State reduction Equivalent state diagrams

State assignment • • • Assign a unique code for each state For a circuit with 𝑚 2 𝑛 ≥ 𝑚 states use 𝑛 bits, where For states remaining use “Don’t care” to help reduce circuit.

State Assignment What code assignment would you choose? Why?

State Assignment Draw the state diagram for this assignment.

Design Procedure 1. From the word description and specifications of the desired operation, derive a state diagram for the circuit.

2. Reduce the number of states if necessary 3. Assign binary values to the states 4. Obtain the binary-coded state table 5. Choose the type of flip-flops to be used 6. Derive the simplified flip-flop input equations and output equations 7. Draw the logic diagram

Design Procedure • Design a circuit that detects a sequence of three or more consecutive 1’s in a string of bits coming through an input line (input is a serial bit string) 0 0 S 0 /0 S 1 /0 0 1 0 1 1 S 1 /0 1 S 1 /0

Synthesis using D flip-flops 𝐴 𝑡 + 1 = 𝐷 𝐴 𝐴, 𝐵, 𝑥 = (3,5,7) 𝐵 𝑡 + 1 = 𝐷 𝐵 𝐴, 𝐵, 𝑥 = (1,5,7) 𝑦( 𝐴, 𝐵, 𝑥 = (6,7)

Synthesis using D f flip-flops Maps for sequence detector Exercise: Draw the logic diagram of sequence detector

Synthesis using D flip-flops

Excitation tables • • • With D flip-flops design is straightforward With JK and T flip-flops input equations must be derived indirectly from the state table Need to derive a functional relationship between the state table and the input equations

Excitation tables

Synthesis using JK flip-flops Question: Why the “Don’t cares”?

Synthesis using JK flip-flops

Synthesis using JK flip-flops

Synthesis using T flip-flops Design an 𝑛 -bit binary counter.

Use 𝑛 flip-flops Can count from 0 to 2 𝑛 State diagram of three-bit binary counter

Synthesis using T flip-flops Discuss with your neighbor classmate this table

Synthesis using T flip-flops Maps for three-bit counter

Synthesis using T flip-flops Logic diagram of three-bit counter

• • • • • 5.5

5.8

5.9

5.12

5.19

Homework assignment