Transcript A New Kind of Algebra

LATCH
Storage
Bi-stability
Latches
ECEn 224
11 LATCH
Page 1
© 2003-2008
BYU
This is
THE END
of Combinatorial Circuits
ECEn 224
11 LATCH
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© 2003-2008
BYU
and
the
beginning
of sequential circuits
ECEn 224
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© 2003-2008
BYU
Sequential Circuits
• The output of a Combinatorial Circuit
depends only on the current inputs
• The output of a Sequential Circuit
depends on the current and past
inputs
ECEn 224
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© 2003-2008
BYU
Sequential Applications
• Do X, then do Y three times, then do Z
• Take the dot product of two vectors, input
one element at a time
• Control a car wash
–
–
–
–
Rinse
Soap
Rinse
Dry
• All of these require memory
– To remember where in the process they are…
ECEn 224
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© 2003-2008
BYU
Bi-Stability
The Key to Memory
This is a stable state –
it will sit like this forever
0
1
0
This is also a stable state –
it will sit like this forever
1
0
1
There are 2 stable states a bi-stable circuit…
ECEn 224
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© 2003-2008
BYU
SR Latch – A Bi-Stable Circuit
R
S
R
S
This is a stable state –
it will sit like this forever
0
0
0
Q
Q’
1
0
1
0
0
This is also a stable state –
it will sit like this forever
Q
Q’
ECEn 224
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© 2003-2008
BYU
SR Latch Transition
R
S
R
S
0
0
1
1
R
1
1
Q
Q’
S
0
0
0
R
Q
0 Q’
S
ECEn 224
1
Q
Q’
0
0
1
0
0
Q
Q’
11 LATCH
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© 2003-2008
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R
SR Latch Timing
A
B
C
0
A
0
Q
D
S
S
R
1
0
1
B
0
R
Q
S
Q’
R
S
t0
1
0
0
C
1
1
0
Q’
Q
Q’
Q
Q’
time
t = t0 + 2 x tNOR
R
0
D
1
Q
t = t0 + tNOR
ECEn 224
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S
Q’
0 © 2003-2008
BYU
0
R
SR Latch Timing
A
B
1
A
1
C
S
S
R
0
1
0
B 0
R
Q
S
Q’
R
t0
S
t1
t = t0 + 2 x tNOR
t = t0 + tNOR
Q
0
0
0
C
1
0
time
t = t1 + 2 x tNOR
t = t1 + tNOR
ECEn 224
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0
© 2003-2008
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Q’
Q
Q’
Q
Q’
SR Latch Transition Table
R
Q
Q’
S
S
R Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q+
0
1
0
0
1
1
?
?
Comment
No change
Reset
Set
The current state of the Q output
The next state of the Q output
(what it will change to)…
ECEn 224
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© 2003-2008
BYU
SR Latch Transition Table
R
Q
Q’
S
S
R Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q+
0
1
0
0
1
1
?
?
No change
Reset it
Set it
The current state of the Q output
The next state of the Q output
(what it will change to)…
ECEn 224
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© 2003-2008
BYU
SR Latch: S=R=‘1’
R
1
S
1
0
0
Q
Q’
Is the latch SET ???
→ no
Is the latch RESET ??? → no
What is it?
→ neither
We avoid this input combination in normal usage,
mainly because it makes no sense.
ECEn 224
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© 2003-2008
BYU
SR Latch Transition Table
R
Q
Q’
S
S
R Q
Q+
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
N/A
N/A
ECEn 224
0
1
0
1
0
1
0
1
No change
Reset it
Set it
Unused
11 LATCH
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SR Latch – Next State Equation
S
R Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q+
SR
0
1
0
0
1
1
X
X
00
Q
0
1
1
01
11
10
X
1
X
1
Q+ = S + R’Q
The next state of Q will be true any time:
• You SET it
• It is already true and you don’t RESET it
ECEn 224
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© 2003-2008
BYU
SR Latches – So What?
• Illustrate simple notion of bi-stability
– Two stable states
– S and R inputs move latch between them
• A memory
– When Q=1  latch storing a ‘1’
– When Q=0  latch storing a ‘0’
• Will hold its value indefinitely
– As long as circuit is powered
ECEn 224
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© 2003-2008
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SR Latches – What Are They Used For?
• Mainly to explain simple storage in
digital design textbooks
• Simple SR latch not used by itself in
designs very much
– Due to some timing issues we will learn
later…
• Simple SR latch forms basis for most
other kinds of storage elements we
will study
ECEn 224
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© 2003-2008
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Symbology
R
Q
S
Q
R Q’
Q’
S
ECEn 224
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© 2003-2008
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Gated Latches
ECEn 224
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SR Latches Always Sampling Inputs
• An SR latch will always respond to
S/R input changes
– ALWAYS!
• Sometimes we want to control when a
storage element changes
– Use a gated latch
ECEn 224
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The Gated SR Latch
R
• When GATE = 0
GR
– GR = GS = 0
– Latch cannot be modified
Q
Q’
S
GS
GATE
• When GATE = 1
– GR = R, GS = S
– Works like an SR latch
Latch
The GATE signal allows us to control
when
the latch will be loaded with a new value
ECEn 224
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© 2003-2008
BYU
Gated SR Latch Timing
GATE=0
Latch ignores inputs
GATE=1
Latch responds to inputs
GATE=0
Latch holds old value
– ignores inputs
GATE
S
R
Q
Q’
time
ECEn 224
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© 2003-2008
BYU
Gated SR Latch Transition Table
R
GR
Q
Q’
S
GS
How many inputs are in
the transition table?
Can you draw it?
GATE
ECEn 224
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© 2003-2008
BYU
Gated SR Latch Transition Table
R
GR
Q
Q’
S
GS
GATE
Gate
S
R
Q
Q+
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
0
1
1
0
1
1
0
X
0
1
1
1
X
1
0
0
0
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
X
1
1
1
1
X
ECEn 224
No
change
possible
Like an
SR Latch
11 LATCH
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© 2003-2008
BYU
Gated SR Latch Next State Equation
R
GATE S
00 01 11 10
RQ
GR
Q
00
01
1
1
1
11
1
X
X
X
X
Q’
S
GS
1
10
GATE
1
Q+ = GATE•S + R’•Q + GATE’•Q
ECEn 224
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© 2003-2008
BYU
Gated SR Latch
• Sometimes known as a loadable SR
latch
– The GATE signal acts like a load input
R
GR
Q
Q’
S
GS
GATE
ECEn 224
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© 2003-2008
BYU
Symbology
S Q
R Q’
Gate
R
Q
or…
Q’
S
S Q
R Q’
Load
GATE
ECEn 224
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© 2003-2008
BYU
The Gated D Latch
D
Q’
Q
GATE
Q+ = GATE•D + GATE’•Q
GATE
D
Q
Q+
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
When GATE = 1  Q follows D
(storage)
When GATE = 0  Q retains old value (retention)
ECEn 224
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© 2003-2008
BYU
Gated D Latch - Timing
Hold last loaded value
Follow D input
Hold value
GATE
D
Q
time
ECEn 224
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© 2003-2008
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Gated D Latches
• Sometimes called a transparent latch
– When GATE = 1, the D input propogates
to Q output
• Allows us to control when to store
new data into latch
– D = data to be stored
– GATE = control signal
ECEn 224
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© 2003-2008
BYU
Gated D Latch – Usage
Storage element
Data to be
stored
D
Q’
Indication
of data
stored
Q
GATE
Store/Load signal
ECEn 224
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© 2003-2008
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Symbology
D Q
D
Gate
or…
Q
D Q
GATE
Load
ECEn 224
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© 2003-2008
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Gated D Latches - Timing
D
Q’
Q
GATE
• If GATE = 1
• When D changes, output will change after:
tDQ = tNOT + tAND + tNOR + tNOR
= tNOT + tAND + 2×tNOR
• Why tNOT ?
• Why 2×tNOR ?
ECEn 224
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© 2003-2008
BYU
Gated D Latches - Timing
D
Q’
Q
GATE
• If D is constant
• When GATE rises (0  1), output will change after:
tGATEQ = tAND + tNOR + tNOR
= tAND + 2×tNOR
• Why no tNOT ?
ECEn 224
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© 2003-2008
BYU
An Example Gated D Latch Circuit
D
Q’
Q
GATE
• When GATE = 1:
• Latch loads Q’ (toggles)
• 0  1 or 1  0
• Is there another way to wire this circuit?
ECEn 224
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© 2003-2008
BYU
Toggle Circuit Timing Diagram
D
Q’
Q
A
GATE
B
GATE
D
Q
oscillation
time
ECEn 224
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© 2003-2008
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Toggle Circuit Problem
• As long as GATE = 1, latch will
repeatedly load new values
– 0→1→0→1→0→1...
• Wouldn’t it be nice if it just loaded once
each time GATE went high?
• Solution #1:
– Make GATE = 1 for a very short time
– Hard to do reliably
• Solution #2:
– Build a new storage element out of gated D
latches (the flip flop  next lecture)
ECEn 224
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© 2003-2008
BYU