Transcript PPT - Computer Science Department Homeage

Latches & Flip-flops
Computer Architecture
CS 215
1
Sequential Circuits
Inputs
Storage
Elements
 Storage
elements

Outputs
Combinat
ional
Logic
State
Next
State
Latches or FlipFlops
 Combinatorial
Logic
2
Sequential Circuits
Inputs
Storage
Elements
 Combinatorial Logic
 Next state function

Next State = f(Inputs,
State)
 Output function (Mealy)
Outputs = g(Inputs,
State)
 Output function (Moore)
Outputs = h(State)
Output function type depends
on specification and affects
the design significantly
Outputs
Combinat
ional
Logic
State
Next
State
3
Sequential Circuits
 Synchronous


Behavior defined from knowledge of its signals at discrete
instances of time
Storage elements observe inputs and can change state only
in relation to a timing signal (clock pulses from a clock)
 Asynchronous



Behavior defined from knowledge of inputs an any instant of
time and the order in continuous time in which inputs
change
If clock just regarded as another input, all circuits are
asynchronous!
Nevertheless, the synchronous abstraction makes complex
designs tractable!
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Discrete Event Simulation
 Rules:




Gates modeled by an ideal (instantaneous)
function and a fixed gate delay
Any change in input values is evaluated to see if it
causes a change in output value
Changes in output values are scheduled for the
fixed gate delay after the input change
At the time for a scheduled output change, the
output value is changed along with any inputs it
drives
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Simulated NAND Gate
 Example: A 2-Input
F(Instantaneous)
A
DELAY 0.5 ns.
B
t (ns)
A
B
–
1
1
0
1 0 1
0 1
0.5
0.8 1 0 1
0.13
1
1
F(I)
0
1 0
F
NAND gate with a 0.5 ns.
delay
 Assume A and B have
been 1 for a long time
 At time t=0, A changes
back to 1. to a 0 at t=
0.8 ns,
F
Comment
0
A=B=1 for a long time
0
F(I) changes to 1
1 0 F changes to 1 after a 0.5 ns delay
1
F(Instantaneous) changes to 0
1 0 1
0 1 0 F changes to 0 after a 0.5 ns delay
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Basic (NAND) S–R Latch
S (set)
 “Cross-
Coupling”
two NAND
gates gives
the S-R Latch
 S = 0, R = 0
is
forbidden as
input pattern
Q
Q
R (reset)
Time R S Q Q Comment
1
1
1
0
1
0
1
1
0
1
1
1
0
1
?
1
1
0
0
1
?
?
0
0
1
1
1
?
Stored state unknown
“Set” Q to 1
Now Q “remembers” 1
“Reset” Q to 0
Now Q “remembers” 0
Both go high
Unstable!
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Basic (NOR) S–R Latch
R (reset)
 Cross-
coupling
two
NOR
gates
gives the Time R
0
S–R
0
Latch
0
1
0
1
0
S (set)
S
0
1
0
0
0
1
0
Q
?
1
1
0
0
0
?
Q
?
0
0
1
1
0
?
Q
Q
Comment
Stored state unknown
“Set” Q to 1
Now Q “remembers” 1
“Reset” Q to 0
Now Q “remembers” 0
Both go low
Unstable!
8
Clocked S-R Latch
 Adding two NAND
gates to the basic
S-R NAND latch
gives the clocked
S–R latch:
S
Q
C
Q
R
 Has a time sequence behavior similar to the basic S-R
latch except that the S and R inputs are only observed
when the line C is high.
 C means “control” or “clock”.
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Clocked S-R Latch
 The Clocked S-R Latch can be described by a table
S
Q
C
Q
R
 The table describes
what happens after the
clock [at time (t+1)]
based on:


current inputs (S,R) and
current state Q(t).
Q(t) S R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+1)
0
0
1
???
1
0
1
???
Comment
No change
Clear Q
Set Q
Indeterminate
No change
Clear Q
Set Q
Indeterminate
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D Latch
D
Q
 Adding an inverter
to the S-R Latch,
gives the D Latch:
 Note that there are
no “indeterminate”
states!
Q
0
0
1
1
D
0
1
0
1
Q(t+1)
0
1
0
1
C
Comment
No change
Set Q
Clear Q
No Change
Q
The graphic symbol for a
D Latch is:
D
Q
C
Q
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Flip-Flops
 Master-slave flip-flop
 Edge-triggered flip-flop
 Standard symbols for storage elements
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S-R Master-Slave Flip-Flop
 Two clocked




S
S
C
C
Q
S
Q
Q
C
S-R latches in series
R
R
Q
with the clock on the
R
Q
Q
second latch inverted
The input is observed
by the first latch with C = 1
The output is changed by the second latch with C = 0
The path from input to output is broken by the difference in
clocking values (C = 1 and C = 0).
The behavior demonstrated by the example with D driven by Y
given previously is prevented since the clock must change from
1 to 0 before a change in Y based on D can occur.
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Edge-Triggered D Flip-Flop
 The edge-triggered
D flip-flop is the
same as the masterslave D flip-flop
D
D
Q
S
Q
Q
Q
Q
C
C
C
Q
R
 It can be formed by:


Replacing the first clocked S-R latch with a clocked D latch or
Adding a D input and inverter to a master-slave S-R flip-flop
 The delay of the S-R master-slave flip-flop can be avoided since
the 1s-catching behavior is not present with D replacing S and R
inputs
 The change of the D flip-flop output is associated with the
negative edge at the end of the pulse
 It is called a negative-edge triggered flip-flop
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Positive-Edge Triggered D
Flip-Flop
 Formed by
adding inverter
to clock input
D
D
Q
S
Q
Q
Q
Q
C
C
C
Q
R
 Q changes to the value on D applied at the positive
clock edge within timing constraints to be specified
 Our choice as the standard flip-flop for most
sequential circuits
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Standard Symbols for Storage
Elements
S
S
D
D
R
R
C
C
SR
 Master-Slave:
Postponed output
indicators
 Edge-Triggered:
Dynamic
indicator
D with 1 Control D with 0 Control
SR
(a) Latches
S
S
C
C
R
R
Triggered SR
Triggered D
Triggered SR
(b) Master-Slave Flip-Flops
D
D
C
D
D
C
C
Triggered D
C
Triggered D
Triggered D
(c) Edge-Triggered Flip-Flops
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State Diagrams
 The sequential circuit function can be represented in
graphical form as a state diagram with the following
components:




A circle with the state name in it for each state
A directed arc from the Present State to the Next State for
each state transition
A label on each directed arc with the Input values which
causes the state transition, and
A label:
 On each circle with the output value produced, or
 On each directed arc with the output value produced.
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State Diagrams
 Label form:

On circle with output included:
 state/output
 Moore type output depends only on state

On directed arc with the output included:
 input/output
 Mealy type output depends on state and input
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State Diagram:
SR Latch
Q(t) S R
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+1)
0
0
1
???
1
0
1
???
Comment
No change
Clear Q
Set Q
Indeterminate
No change
Clear Q
Set Q
Indeterminate
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Other Flip-Flop Types
 J-K and T flip-flops


Behavior
Implementation
 Basic descriptors for understanding and using
different flip-flop types
Characteristic tables
 Characteristic equations
 Excitation tables
 For actual use, see Reading Supplement - Design and
Analysis Using J-K and T Flip-Flops

20
J-K Flip-flop
 Behavior





Same as S-R flip-flop with J analogous to S and K
analogous to R
Except that J = K = 1 is allowed, and
For J = K = 1, the flip-flop changes to the opposite
state
As a master-slave, has same “1s catching”
behavior as S-R flip-flop
If the master changes to the wrong state, that
state will be passed to the slave
 E.g., if master falsely set by J = 1, K = 1 cannot reset it
during the current clock cycle
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J-K Flip-flop
 Implementation

To avoid 1s catching behavior, one
solution used is to use an edgetriggered D as the core of the flipflop
J
C
K
Build
this!
JK=00
J
K
D
JK=10 or 11
Q=0
JK=00
Q=1
C
JK=01 or 11
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T Flip-flop
 Behavior

Has a single input T
 For T = 0, no change to state
 For T = 1, changes to opposite state
 Same as a J-K flip-flop with J = K = T
 As a master-slave, has same “1s catching”
behavior as J-K flip-flop
 Cannot be initialized to a known state using
the T input

Reset (asynchronous or synchronous) essential
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T Flip-flop
 Implementation

To avoid 1s catching behavior, one
solution used is to use an edgetriggered D as the core of the flipflop
T
C
Build
this!
T
D
T=1
T=0
T=0
Q=1
Q=0
C
T=1
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Basic Flip-Flop Descriptors
 Used in analysis


Characteristic table - defines the next state of the
flip-flop in terms of flip-flop inputs and current
state
Characteristic equation - defines the next state of
the flip-flop as a Boolean function of the flip-flop
inputs and the current state
 Used in design

Excitation table - defines the flip-flop input variable
values as function of the current state and next
state
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D Flip-Flop Descriptors
 Characteristic Table
D
Q(t + 1) Operation
0
1
0
1
Reset
Set
 Characteristic Equation
Q(t+1) = D
 Excitation Table
Q(t +1)
D
Operation
0
1
0
1
Reset
Set
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T Flip-Flop Descriptors
 Characteristic Table
T Q(t +1)
Operation
0
Q(t)
No change
1
Q(t)
Complement
 Characteristic Equation
Q(t+1) = T  Q
 Excitation Table
Q(t +1)
T
Operation
Q(t)
0
No change
Q(t)
1
Complement
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S-R Flip-Flop Descriptors
 Characteristic Table
S R Q(t +1) Operation
0 0
0 1
1 0
Q(t)
0
1
No change
Reset
Set
1 1
?
Undefined
 Characteristic Equation
Q(t+1) = S + R Q, S.R = 0
Q(t) Q(t+ 1)
 Excitation Table
S R Operation
0
0
1
0
1
0
0 X No change
1 0 Set
0 1 Reset
1
1
X 0 No change
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J-K Flip-Flop Descriptors
 Characteristic Table
J K Q(t+1)
Operation
0
0
1
1
No change
Reset
Set
Complement
0
1
0
1
Q(t)
0
1
Q(t)
 Characteristic Equation
Q(t+1) = J Q + K Q
 Excitation Table
Q(t)
0
0
1
1
Q(t +1) J K Operation
0
1
0
1
0
1
X
X
X
X
1
0
No change
Set
Reset
No Change
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