Transcript Project Traffic Light Controller

Project Traffic Light Controller
Prawat Nagvajara
Goals: To design and synthesize a controller
(FPGA) that interfaces with a virtual
traffic (java animation). We will design
1. Handshake protocol
2. Timer
3. Finite State Machine
Traffic at an Intersection
The Setup of The TLC Problem
Controller (FPGA)
The Remote Site
Problem Statement
• Design a controller for the virtual traffic scenario
– an intersection with no turns
• The controller changes the flow of the traffic if
there is a car waiting on-red and the traffic flow in
the present direction has been longer than a
specified duration
• Parameters: green-light duration and yellow-light
duration
• Signals:
– To remote site: change_light
– From remote site: car_waiting and acknowledge
Xilinx FPGA Design Flow
• VHDL code and simulation
– Synthesis
• Mentor Graphics leonardo tool, invoking command,
leonardo or
• Xilinx Foundation tools: synthesis
– Implementation using Xilinx Foundation to
FPGA hardware code
– Download compiled code (.bit file) to an FPGA
demo board
User Constraint File - Pins Definition
• Associate signals and pins use this project_name.ucf file
NET reset LOC = P28;
NET car_waiting LOC = P20;
NET acknowledge LOC = P24;
NET change_sim_light LOC = P70;
NET change_real_light LOC = P60;
• All signals are active-low
• Change_real_light toggles (between ‘0’ and ‘1’) in
turn triggers a transition of the physical lights.
• Reset for setting the controller to a known state
(RedGreen)
• In the initial state (RedGreen), Change_real_light is
‘0’
Internal Oscillator of XC4000E
component osc4
port (
F8M : out std_logic;
F500K: out std_logic;
F16K : out std_logic;
F490 : out std_logic;
F15 : out std_logic);
end component;
Partially Completed VHDL Code
• Contains declaration of signals and
components
• Need to complete the FSM portion
• FSM handles the handshake protocol, I.e.,
change light request and acknowledgement
• Contains VHDL code for timer