Transcript Lecture 10 RTL Design Methodology Sorting Example Required reading • P. Chu, FPGA Prototyping by VHDL Examples Chapter 6, FSMD • S.

Lecture 10
RTL Design Methodology
Sorting Example
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 6, FSMD
• S. Brown and Z. Vranesic,
Fundamentals of Digital Logic with VHDL Design
Chapter 10.2, Design Examples
ECE 448 – FPGA and ASIC Design with VHDL
2
Structure of a Typical Digital
System
Data Inputs
Control & Status Inputs
Control
Signals
Datapath
(Execution
Unit)
Controller
(Control
Unit)
Status
Signals
Data Outputs
Control & Status Outputs
Hardware Design with RTL VHDL
Pseudocode
Interface
Datapath
Block
diagram
VHDL code
Controller
Block
diagram
VHDL code
State diagram
or ASM chart
VHDL code
Steps of the Design Process
1.
2.
3.
4.
5.
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
6. ASM chart of the Controller
7. RTL VHDL code of the Datapath, the Controller, and the
Top Unit
8. Testbench of the Datapath, the Controller, and the Top
Unit
9. Functional simulation and debugging
10. Synthesis and post-synthesis simulation
11. Implementation and timing simulation
12. Experimental testing
Steps of the Design Process
Practiced in Class Today
1.
2.
3.
4.
5.
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
6. ASM chart of the Controller
7. RTL VHDL code of the Datapath, the Controller, and the
Top Unit
8. Testbench of the Datapath, the Controller, and the Top
Unit
9. Functional simulation and debugging
10. Synthesis and post-synthesis simulation
11. Implementation and timing simulation
12. Experimental testing
Sorting
example
Sorting - Required Interface
Clock
Resetn
N
N
DataIn
DataOut
L
RAdd
Sorting
WrInit
S
(0=initialization
1=computations)
Rd
Done
Sorting - Required Interface
Simulation results for the sort operation (1)
Loading memory and starting sorting
Simulation results for the sort operation (2)
Completing sorting and reading out memory
Sorting - Example
Before
sorting
Address
0
1
2
3
Legend:
3
2
4
1
During Sorting
i=0
j=1
i=0
j=2
i=0
j=3
i=1
j=2
i=1
j=3
i=2
j=3
3
2
4
1
2
3
4
1
2
3
4
1
1
3
4
2
1
3
4
2
1
2
4
3
position of memory
indexed by i
Mi
position of memory
indexed by j
After
sorting
1
2
3
4
Mj
Pseudocode
FOR k = 4
[load input data]
for i = 0 to 2 do
A = Mi ;
for j = i + 1 to 3 do
B = Mj ;
if B < A then
Mi = B ;
Mj = A ;
A = Mi ;
endif ;
endfor;
endfor;
[read output data]
FOR any k ≥ 2
[load input data]
for i = 0 to k -2 do
A = Mi ;
for j = i + 1 to k – 1 do
B = Mj ;
if B < A then
Mi = B ;
Mj = A ;
A = Mi ;
endif ;
endfor;
endfor;
[read output data]
Pseudocode
wait for s=1
for i=0 to k-2 do
A = Mi
for j=i+1 to k-1 do
B = Mj
if A > B then
Mi = B
Mj = A
A = Mi
end if
end for
end for
Done
wait for s=0
go to the beginning
DataIn
RAdd
0
ABMux
N
1
0
1
N
EA
EN
CLK
RST
L
Resetn
Lj
Ej
Clock
LD
EN
CLK
RST
L
j
1
Mij
EB
Clock
Clock
i
0
CLK
DOUT
EN
CLK
Resetn
= k-2
= k-1
zi
zj
RST
N
N
0
L
ADDR
Clock
Resetn
+1
0
Addr
Wr
RST
Csel
WE
1
Clock
s
DIN
We
LD
EN
CLK
Li
Ei
s
Din
WrInit
L
L
N
Rd
N
Bout
B
A
A>B
AgtB
DataOut
Block diagram of the Datapath
Resetn
Interface with the division into
the Datapath and the Controller
DataIn RAddr WrInit
N
Rd
Clock Resetn
s
L
AgtB
zi
zj
Datapath
Wr
Li
Ei
Lj
Ej
EA
EB
Bout
Csel
Controller
N
DataOut
Done