Transcript Document

Custom Single Purpose
Processors: Hardware
Outline
Chapter 2: Custom singlepurpose processors
 Introduction
 Combinational logic
 Sequential logic
 Custom single-purpose processor design
 RT-level custom single-purpose processor design
Custom single-purpose
processor basic model
external
data
inputs
…
external
control
inputs
…
external
control
inputs
…
external
data
inputs
…
controller
datapath
control
inputs
…
datapath
control
outputs
external
control
outputs
datapath
registers
datapath
next-state
and
control
logic
…
state
register
functional
units
external
data
outputs
controller and datapath
Control datapath I/O
Monitor external I/O
controller
Store and manipulate
system data
• registers
• functional units
• wires
• multiplexers
…
…
external
control
outputs
external
data
outputs
a view inside the controller and datapath
int x,y
Example: greatest
common divisor
Our single purpose is to design a GCD!
 Describe in words  Behavioral
design
 Determine I/O Black box view
 Create algorithm
 Convert algorithm to “complex” state
machine
 Known as FSMD: finite-state machine
with datapath  Essentially a flow
chart
 Different than earlier state diagrams
• Arithmetic expressions are allowed
• Other variables are allowed
 Can use templates to perform such
conversion
1
x_i
!(!go_i)
2:
!go_i
(a) black-box
view
go_i
!1
1:
2-J:
y_i
3:
x = x_i
4:
y = y_i
GCD
d_o
(c) state
diagram
!(x!=y)
5:
(b) desired functionality
x!=y
6:
x<y
How would you
implement a
GCD in
software?
7:
y = y -x
8: x = x - y
6-J:
5-J:
9:
1-J:
!(x<y)
d_o = x
State diagram templates
Assignment statement
Loop statement
Branch statement
if (c1)
c1 stmts
else if c2
c2 stmts
else
other stmts
next statement
while (cond) {
loop-bodystatements
}
next statement
a=b
next statement
Action of
this state
a=b
next
statement
Condition C:
state C
C:
cond
loop-bodystatements
Loop body
Join
state J
!cond
J:
c1
c1 stmts
!c1*c2
c2 stmts
J:
next
statement
next
statement
!c1*!c2
others
Creating the datapath
 Create a register for any declared
variable  x, y, d
 Create a functional unit for each
arithmetic operation
 Connect the ports, registers and
functional units
 Based on reads and writes
 Connect “write’s” source to that
variable’s register
 A source may be an input port,
functional unit or other registers
 Use multiplexers for multiple 7:
sources
 Create unique identifier
 for each datapath component
control input and output
!1
1:
1
!(!go_i)
2:
!go_i
x_i
y_i
2-J:
Datapath
3:
x = x_i
4:
y = y_i
!(x!=y)
5:
0: x
0: y
x!=y
6:
x<y
y = y -x
8: x = x - y
9: d
6-J:
5-J:
9:
1-J:
!(x<y)
d_o
d_o = x
FSMDFSM
 In order to implement this design, we need to convert the FSMD into
a regular FSM that simply consists of Boolean functions and I/O
variables (along with control I/O).
 Essentially same structure as FSMD
 Replace complex actions/conditions with datapath configurations
 Replace every variable write by actions that set the select signals of the MUX
in front of that variable’s register, such that the write’s source passes through
the MUX, and assert the load signal of that register.
 Replace every logical operation in a condition by the corresponding functional
unit control output
 Any signal that is not explicitly assigned a state, is implicitly
assigned a zero (0), e.g., x_ld is assigned a 0 in every state, except
for 3 and 8, where it is assigned a “1”
Creating the controller’s FSM
go_i
!1
1:
Controller
0000
1
!(!go_i)
2:
1:
1
0001
!(!go_i)
2:



!go_i
!go_i
2-J:
3: x = x_i
4: y = y_i
!(x!=y)
5:
!1
0010
2-J:
0011
3:
0100
4:

Same structure as FSMD
Replace complex actions/conditions with
datapath configurations
Replace every write by actions that set the select
signals of the MUX in front of the variable’s reg.,
and assert the load signal of that reg.
Replace every logical operation in a condition by
the corresponding functional unit control output
x_i
y_i
Datapath
0101
5:
0110
6:
x!=y
6:
x_ld
x<y
!(x<y)
7: y = y -x 8: x = x - y
6-J:
5-J:
9: d_o = x
0: x
0: y
y_ld
7:
8:
0111
1000
1001
6-J:
1010
5-J:
1011
9:
9: d
d_ld
d_o
1-J:
1100
1-J:
Implementing the FSM
 Complete the controller design by implementing the FSM we have just created
 Use the standard sequential design techniques for this purpose




Complete the state diagram
Create the transition table
Generate Boolean functions from the transition table
Controller implementation model
Simplify the Boolean expressions, etc.
 Note that in the previous design, there were
a total of 13 states, which in general,
requires 4 FFs  hence 4 state variables,
I1, I2, I3, I4, with outputs Q1 ~ Q4.
go_i
Combinational
logic
x_sel
y_sel
x_ld
y_ld
x_neq_y
x_lt_y
d_ld
Q3 Q2 Q1 Q0
State register
I3
I2
I1
I0
Splitting into a controller and
datapath
go_i
Controller
0000
!1
1:
1
Controller implementation model
go_i
0001
y_sel
x_ld
y_ld
Datapath
!go_i
x_sel
0010 2-J:
0011
3:
State register
I3
I2
I1
I0
n-bit 2x1
x_sel = 0
x_ld = 1
x_ld
0: x
0: y
y_ld
0100
4:
0101
5:
d_ld
Q3 Q2 Q1 Q0
n-bit 2x1
y_sel
x_neq_y
x_lt_y
y_i
2:
x_sel
Combinational
logic
x_i
!(!go_i)
0110
6:
x_lt_y=1
7: y_sel = 1
y_ld = 1
y_sel = 0
y_ld = 1
x_neq_y=1
x_lt_y=0
x_sel
=1
8:
x_ld = 1
0111
1000
1001
6-J:
1010
5-J:
1011
9:
1100
1-J:
!=
x_neq_y=0
d_ld = 1
5: x!=y
x_neq_y
x_lt_y
<
6: x<y
subtractor
8: x-y
subtractor
7: y-x
9: d
d_ld
d_o
Controller state table for the
GCD example
Inputs
0
0
0
0
1
1
0
1
0
1
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
0
0
0
0
X
X
X
X
0
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
1
X
X
X
X
X
X
X
X
d_ld
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
0
0
0
0
y_ld
*
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Controller
O/P variables
x_ld
*
*
*
*
*
*
*
*
0
1
*
*
*
*
*
*
*
*
*
y_sel
*
*
*
*
*
*
0
1
*
*
*
*
*
*
*
*
*
*
*
x_sel
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
I0
x_lt_y
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
I1
Q0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
Next state
values
I2
Q1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Outputs
I3
Q2
x_neq_y
go_i
Q3
Current state
values
Controller
I/P variables
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Other issues…
 There are a total of 7 inputs to the controller 128 rows for TT
 Reduce number of rows, using * for some I/P combinations
 Tedious to optimize by hand
 Use CAD tools !
 CAD tools that automatically generate digital gates from sequential programs
(behavioral design), FSMDs or FSMs or logic equations are known as sythesis tools.
 Data path can also be further optimized:
 Merge functional units (one instead of two subtractors), but we would then need more
multiplexers.
 Merge certain states into single states
 Be careful about timing issues:
 All statements in a single state are implemented concurrently in an FSMD!
 Actions consisting of writes to variables do NOT actually update the variables until
after the next clock cycle, since all variables are implemented as registers. Assuming
that an outgoing arc from a state is using the updated value is a very common mistake.
If we want to assign a value to a variable, and then branch based on that value, we
NEED to insert an additional state. This is what the empty states in FSMD are for.!
Completing the GCD custom singlepurpose processor design
…
…
controller
 We finished the datapath
 We have a state table for the
next state and control logic
 All that’s left is combinational
logic design
 This is not an optimized design,
but we see the basic steps
datapath
next-state
and
control
logic
registers
state
register
functional
units
…
a view inside the controller and datapath
…
Summary
 Custom single-purpose processors
 Straightforward design techniques
 Can be built to execute algorithms
 Typically start with FSMD
 CAD tools can be of great assistance