Multiplication Units for the Implementation of the ISRA Algorithms Julio A. Sosa, Javier Morales, Nayda Santiago Center for Subsurface Sensing and Imaging Systems University of Puerto Rico at Mayagüez, P. O. Box 9042, Mayagüez, Puerto Rico 00681 ABSTRACT

The Image Space Reconstruction Algorithm (ISRA) is an iterative method used to solve the abundance estimation problem in the analysis of hyperspectral images. A software algorithm was developed that uses ISRA to approximate the abundance in a set of hyperspectral images, however, the execution time of this application is very large. To solve this problem we start with the port of the ISRA algorithm to FPGAs seeking a boost in performance by reducing execution time. Burdensome and time consuming floating point operation blocks were identified and already two of these units had been successfully ported. One of these units is the Floating Point Multiplier that consist of parameterized building blocks that allows us to reuse components instead of create new ones, giving us the advantage of area reduction on the design.

IMAGE SPACE RECONSTRUCTION ALGORITHM

Multispectral/hyperspectral remote sensing image data is useful for discriminating, classifying, identifying as well as quantifying materials present in the image. The precise spectral information contained in a hyperspectral image enables better characterization and identification of targets. Abundance estimation allows one to detect concentrations of different signature spectra present in pixels. One of the algorithms capable of reconstructing from 3-D back-projected images is the Image Space Reconstruction Algorithm (ISRA) 1 .

The ISRA algorithm is an iterative, multiplicative method that is given by the equation:

TOOLS AND DEVICES

During the initial stages of this project, several options were studied and taken into consideration, including the use of DSPs, FPGA’s, and hardware/software codesign techniques.

Active VHDL, Xilinx Virtex II Pro and Virtex IV FPGAs were selected for implementing the ISRA algorithm.

Aldec Active HDL

VHDL is stands for V(ery high speed integrated circuit) H(ardware) D(escription) L(anguage) and it is used to design and model digital electronic systems. It is a very flexible language that allows the designer to create a digital design in a variety of ways. Active HDL is a software that allows us to use VHDL and provides useful features such as block diagram and state diagram editors, waveform and timing diagram simulators and the ability to convert block and state diagrams into source code.

Xilinx ISE 6

Synthesis is the process of constructing a gate level netlist from a model of a circuit described in VHDL.

Xilinx ISE 6 is a popular synthesis tool that allows us to do so. In addition to synthesizing VHDL source code, Xilinx ISE 6 allows us to carry out critical path and delay analysis, as well as doing more advanced analysis and processes through the use of TCL scripts.

X

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j k

 1 

X

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j k i m

  1

b i i m

  1

a ij a i T a ij X

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k

Figure 1. ISRA Algorithm

ISRA has relatively slow convergence rate when compared to other estimators such as the Expectation Maximization – Maximum Likelihood (EMML) algorithm.

FLOATING POINT MULTIPLIER

The floating point multiplier unit in fact is not complicated, neither is the most simplest of the arithmetic operations. The mantissas of the two operands are multiplied using a fixed point multiplier and the exponents are summed and then the extra bias is removed from the value of the exponent addition. The sign bit of the result is the XOR of the operand sign bits. It is very important to note that in these operations the implied ’1’ of each mantissa is pretended at the outset of the computation and then removed after its completion before the result is stored.

s3  m3  2 exp3  s1  m1  2 exp1  s2  m2  2 exp1 s3  s1  s2 m3  m1  m2 exp3  exp1  exp2 127(  1)

Figure 2. Floating Point Multiplication Algorithm

The three components of the floating point result (sign, exponent, and mantissa) can be computed independently 2 .

First, m3 would be a 48-bit number. It must be reduced to a 24-bit number to be stored in the IEEE format and second, the subtraction of 127 is necessary since the exponent for each input is in excess-127 notation.

Figure 3. Synthesized Floating Point Multiplication Unit Field Programmable Gate Array

An FPGA is a chip composed of programmable logic gates. These gates can be set to behave or perform certain task by using VHDL to specify and design the circuit and afterwards synthesizing and optimizing the logic circuit prior to downloading it to an FPGA. An FPGA development board can vary in form and content: peripherals, ports, hardware, etc.

RELEVANCE TO CENSSIS STRATEGIC RESEARCH PLAN

•The ISRA algorithm will be used for coral (SeaBED) image understanding (R2) and its hardware implementation will allow faster information management (R3).

•The hardware implementation of ISRA will aid in monitoring Coral reefs health in coastal shallow waters and other underwater habitats (S4).

METHODOLOGY

The floating point libraries developed in VHDL by Pavle Belanovic 3 and that are available to be distributed under GNU General Public License were used. These files where adapted to our necessities.

• First the operands where defined under the single 32 –bit precision representation.

• The unit that handle the multiplication were lightly modified to includes the implicit 1 that these number have in there MSB position and that is very important to be present before the operation take place.

• Also the multiplication of two 24-bit numbers produces a 48-bit result. Since the format only stores 24 bits of significance, only the upper 24 bits of the result are required. By modifying the algorithm slightly, we can retaining them 4 .

• The exponents are manipulated by a simple adder and a subtraction unit handles the bias.

• Other features specified by the IEEE specification are exception conditions and exception handling. The implementation can be enhanced in the future to correctly handle these exceptions. •We do not to deal with this exception because it is possible to test the data before sending it to the FPGA , to know if a NaN is likely to be in the it.

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FUTURE WORK

• The development of a Graphic User Interface (GUI) to be used to interpret the results and to easly export data to the FPGA.

• The development and implementation of a Floating Point Divider • Continue development of hardware Components • Physical Testing of the system.

ACKNOWLEDGEMENT

We would like to thank professor Miriam Leeser at Northeastern University and her research group for their assistance.

REFERENCES

1. Rosario, Samuel, Arithmetic”, “Iterative Algorithms for Abundance Estimation on Unmixing of Hyperspectral Imagery”, MS Thesis, University of Puerto Rico, Mayagüez Campus, 2004.

2. Prof. W. Kahan, “IEEE Standard 754 for Binary Floating-Point Elect. Eng. & Computer Science University of California Berkeley CA 94720-1776 Lecture Notes on the Status of IEEE 754 October 1, 1997 3:36 am 3. Belanovic, Pavle; Leeser, Miriam; “A Library of Parameterized Floating-Point Modules and Their Use”, Lectures Notes in Computer Science, Volume 2438/2002 Page 657.

4. Louca, L.; Cook, T.A.; Johnson, W.H.; “Implementation of IEEE single precision floating point addition and multiplication on FPGAs”, Proceedings. IEEE Symposium on Custom Computing Machines, 17-19 April 1996 Page(s):107 – 116 5. Lee, B.; Burgess, N.; “Parameterisable floating-point operations on FPGA”,, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, Volume 2, 3-6 Nov. 2002 FPGAs Page(s):1064 - 1068 vol.2

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This work was supported in part by CenSSIS, the Center for Subsurface Sensing and Imaging Systems, under the Engineering Research Centers Program of the National Science Foundation (Award Number ECE-9986821).