Transcript Xilinx Template (light) rev

What are FPGA Power Management
Design Techniques?
Objectives
After completing this module, you will be able to:
Explain why you should target as much of the hard IP as
possible
Describe how your design’s power consumption is dependent on
your use of control signals
Explain how some common design techniques can improve your
design’s power consumption
Use the newest architecture features to improve your design’s
power consumption
Goal: Reduce Power Consumption
Reduce design size
– Reduce the logic and routing resources your design uses
– Manage which logic resources are used
• Instantiate and properly infer the best design resources
– Manage what control signals your design will use
– Don’t trust your synthesis results…manage the results
Hard-IP Blocks
Low
Power
Design
Techniques
Reduces Static Power
– Minimum transistor count
SW Power
Optimization
Power
Estimation Tools
Dedicated
Hard-IP
Dedicated Hard IP
Product Architecture
Process Technology
Reduces Dynamic Power
– Metal Interconnects vs. Metal and programmable
interconnects
– Reduced trace lengths
Static and dynamic power is minimized by using
Hard-IP
Use the Smallest Device Possible
Look for opportunities to reduce logic
– Time slicing of logic functions (2X frequency, ½ logic)
• In general, dynamic power improves due to more than 2X
capacitance drop
Move functions to dedicated hardware resources
–
–
–
–
State machinesBRAMs
CountersDSP48s
Registers  SRLs
BRAMs  LUTRAMs
Tactics to Reduce Power
One of the side benefits of reducing the number of
LUTs and FFs your design uses is that it also allows
you to improve design speed
Do not over-constrain the design during synthesis
– Promotes logic replication
– Use your synthesis options carefully
The 6-input LUT allows you to pack more logic into a
LUT
– However, synthesis tools cannot remove added pipeline
registers
– If your design is migrating from another FPGA you may need
to remove added pipeline registers
Control Signals Problems
Instantiation of primitives and cores
– Gate-level connection of UNISIM and core primitives dictates control signal
usage
– Be aware that some IP available from the CORE Generator does not
necessarily follow these guidelines
– Make certain that you can share the control signals between your design
and your COREs
Synthesis optimization
– Synthesis may choose to build a control signal for logic optimization
– This will be a problem if the control signal has a high fanout
Avoid Active-Low Control Signals
Active-low control signals can produce sub-optimal results
– Control ports on registers are active-high
– Hierarchical design and design re-use can propagate bad design practices
(if the design uses active-low control signals)
This results in…
– More LUTs and routing being used than necessary
– This requires additional inverters at all lower leaf levels
– Worse timing and power
Physical synthesis, design hierarchy, and incremental design
practices
– Can change control sets from the original specifications (be careful)
– Global or logic optimization synthesis settings may choose to build a
control signal for logic optimization
Use Active-High Control Signals
Flip-Flop
The inverters
cannot be
combined into
the same slice
This consumes
more power and
makes timing
difficult
Hierarchical design methods can proliferate LUT
usage on active-low control signals
Design Tips
FF1
Suggestions for faster and smaller designs
– Use synchronous Set/Reset whenever possible
– Use active-high CE and Set/Reset (no local inverter
for secondary control signals)
D
CE
CK
SR
– Try to build your design with as few control signals
as possible
●●●
Rules to recognize
– Clocks and asynchronous set/resets always connect
to the control port of the FF
– Asynchronous sets/resets have priority access to the
control ports over synchronous sets/resets
– Clock enables and synchronous set/resets can
become control signals
Q
FF8
D
CE
CK
Q
SR
Minimizing the Use of DCMs or PLLs
Case A – Embedded DCM
Case B – External DCM
DCM or PLL
In-1
In-1
Logic and Flip-flops
DCM
In-x
In-x
• DCMs are a limited
resource
• DCMs consume a lot of
power
• Using fewer DCMs saves
global clock buffers
Pulling buried DCMs or PLLs up to the top level
reduces power
Reducing Clock and Block Activity
Use BUFGMUX to shutoff global clock when possible
– Reduces switching of circuit
Use BUFCE or BUFHCE to dynamically gate a clock
– Saves routing
– Reduces switching of circuit
Use local clock enables to eliminate extra
FF/BRAM/DSP toggling
– This will save routing resources
FF/BRAM/D
SP
BUFGMUX
BUFGCE
Turning a resource off saves dynamic power
Summary
Reduce your design size
– Target the dedicate IP as much as possible
• Hopefully, this will help you target as small a device as possible
– Do not over-constrain your design (forces logic replication)
– Remove unnecessary pipeline stages (especially if migrating a design)
– Minimize your design’s control signals
– Understand the control signals needed by your COREs
• Share these control signals with the rest of your design, if possible
–
–
–
–
Use active-high control signals
Use synchronous sets/resets
Minimize DCM or PLL use in lower power applications
Use the BUFGMUX, BUFCE, and BUFHCE primitives to reduce
unnecessary toggling and dynamic power consumption
Where Can I Learn More?
Xilinx online documents
– www.support.xilinx.com
• Spartan-6 FPGA Power Management User Guide, UG394
 Introduces the Suspend and Hibernate modes
 Describes the necessary voltage supplies
 Introduces the low-power (-1L) devices
 Describes the Power-On and Power-Down behavior
 Power Estimation options are discussed
• Power Consumption in 65 nm FPGAs, WP246
 Very useful resource to clarify this presentation
Where Can I Learn More?
Xilinx Education Services courses
www.xilinx.com/training
– Designing with Spartan-6 and Virtex-6 Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
Free Video Based Training
– How Do I Plan to Power My FPGA?
– Power Estimation
– What are the Spartan-6 Power Management Features?
– What are the Virtex-6 Power Management Features?
– What are FPGA Power Management HDL Coding Techniques?
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