Transcript Xilinx Template (light) rev

What are the Power Requirements of
My FPGA?
Objectives
After completing this module, you will be able to:
Describe your FPGAs power requirements
Explain how power is used in an FPGA
Explain how your power consumption depends on BOTH your
design and the FPGA device you have chosen
Justify how power consumption in an ASIC is different than an
FPGA
Explain why you need to manage your power consumption
Programmable Logic Devices
Non-programmable logic devices (ASICs, ASSPs, etc)
– Have a pre-defined functionality
– Predictable Power Consumption
• Logic resources are fixed
FPGAs
– Power Consumption is design dependent
• That is because the amount of CLB resources, dedicated
hardware, and routing used is design dependent
– This uncertainty is alleviated by Power Estimation tools
– Modeling a design for power before the design is done
• Needs a certain level of implementation detail that is not
obvious
Estimating Power Consumption
Power calculations can be performed at three distinct phases of
the design cycle
– Concept phase: A rough estimate of power can be calculated based on
estimates of logic capacity and activity rates
• Use the Xilinx Power Estimator spreadsheet
– Design phase: Power can be calculated more accurately based on detailed
information about how the design is implemented in the FPGA
• Use the XPower Analyzer
– System Integration phase: Power is calculated in a lab environment
• Use actual instrumentation
Accurate power calculation at an early stage in the design cycle
will result in fewer problems later
Why Reduce Power?
Thermal Impact
Non-Virtex
Virtex
– Simpler system thermal design
– No airflow, fans or heatsinks
Power Supply Choice
No Heat Sinks
Non-Virtex
– Smaller supply circuitry
– Reduced components
– Less PCB space
Higher system reliability
Virtex
Smaller Power Supplies
– MTTF rises with temperature
Overall lower cost
Powering an FPGA
It takes 3 distinct power supplies to power the
contemporary FPGAs
– Different voltages for different transistors
• Configuration circuits -- Vccaux
• FPGA Core -- Vccint
• I/O Banks – Vcco
– Different Noise level requirements
Vcco power all outputs (single-ended and differential)
Vccint powers all architectural elements and some
inputs
Vccaux powers configuration circuitry, DCM and
differential inputs
Thermal Impact of Power
Performance
And
Density
Die Temp
Higher Power  rise in operating
temperature or Junction
Temperature (Tj)
Exceeding the Tj max spec leads to
150 oC
125 oC
100 oC
– Reduced system performance
– Reduced device reliability
So, there is not a Max total Power
specification for FPGAs!
– The indirect limit is the operating Tj
spec
Junction temperature is limited to
– 85oC for Commercial grade devices
– 100oC for Industrial grade devices
Start-Up Power
Inrush Currents
– Ambiguous status of SRAM cells
at start up can cause contention
– Results in current spikes / surges
– Xilinx has eliminated these through
innovative house keeping circuitry
Configuration Current
– After power up there is a need for
power during configuration
– Power Supplies must provide at
least this minimum amount of
current for successful power-up
and configuration
Summary
There are 3 necessary power sources for your FPGA
– Vcco, Vccint, and Vccaux
Power consumption has a static and dynamic element in an
FPGA
– Static power is used to supply the quiescent current necessary for each
power source
– Dynamic power is dependent on the operation of your design (toggle rates,
etc.)
ASIC power consumption is more predictable because the device
has been optimized to minimize unused resources
You need to manage your power consumption to avoid adding
heat sinks, adding airflow, using a more expensive power supply,
improve system reliability, and build at the lowest cost
Where Can I Learn More?
Xilinx online documents
– www.support.xilinx.com
• Spartan-6 FPGA Power Management User Guide, UG394
 Introduces the Suspend and Hibernate modes
 Describes the necessary voltage supplies
 Introduces the low-power (-1L) devices
 Describes the Power-On and Power-Down behavior
 Power Estimation options are discussed
Where Can I Learn More?
Xilinx Education Services courses
www.xilinx.com/training
– Designing with Spartan-6 and Virtex-6 Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
Free Video Based Training
– How Do I Plan to Power My FPGA?
– Power Estimation
– What are the Spartan-6 Power Management Features?
– What are the Virtex-6 Power Management Features?
– Basic FPGA Configuration, Parts 1 and 2
Trademark Information
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on,
or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded,
displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or
otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of
privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,
copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no
obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH
YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE,
WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS,
IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH
YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF
FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT
THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU
WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe
controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons
systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You
represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.