Transcript Xilinx Template (light) rev

How to Convert ASIC Code to FPGA Code
Part 1
Intro to VHDL or
Intro to Verilog
3
days
FPGA and ASIC
Technology Comparison
Curriculum
Path
FPGA vs. ASIC
Design Flow
ASIC to FPGA Coding
Conversion
Virtex-5 Coding Techniques
Spartan-3 Coding Techniques
Fundamentals of
FPGA Design
Designing for
Performance
for
1
day
2
days
Advanced FPGA
Implementation
ASIC Design
2
days
Welcome
If you are an experienced ASIC designer transitioning to FPGAs,
this course will help you reduce your learning curve by
leveraging your ASIC experience
Careful attention to how a design can be optimized for an FPGA,
will help you create a fast and reliable FPGA design
After completing this module, you will able to:
Optimize ASIC code for implementation in an FPGA
Describe the steps to perform ASIC to FPGA code conversion
Xilinx FPGA Optimization
To obtain the desired performance and area goals, the design
needs to be optimized for a Xilinx FPGA
Xilinx FPGAs contain special resources that provide for better
performance and optimization
– DCM, block RAM, global clock routing resources, and clock enable ports,
for example
Use synchronous design methodology for performance and
reliability
Some resources need to be instantiated
– Some resources cannot be inferred
• Startup block, DCM, and SelectIO™ interfaces, for example
Xilinx-Specific Resources
Inference
– Check your synthesis tool’s solutions database—often best for primary
logic resources
Instantiation (from the Architecture Wizard)
– Best for SERDES (ChipSync™ Wizard), DCM (DCM Wizard), or PLL
components
Instantiation (from the Core Generator™ tool)
– Best for DSP, block RAM, larger components, and custom components
Instantiation (from the Memory Interface Generator)
– Best for memory controllers
Instantiation (from the Xilinx Unified Library)
– Best for startup blocks, I/O buffers, or ANY resource
Instantiation Rules
Rule of thumb: Instantiate only when you cannot infer a proper
resource or when inference does not provide acceptable results
Each synthesis tool requires different resources to be
instantiated,
while others can infer resources if an additional synthesis tool
attribute
is applied
– So check your vendors solution data base (Exemplar, Synopsys, and XST)
Synthesis Settings
Synthesis tools help you to achieve higher performance by
– Duplicating registers and logic to reduce fanout
– Extracting state machines to re-encode for one-hot, gray, binary, or twohot encoding
– Replicating the IOB three-state register
• Allows the register to be placed in the IOB by providing faster clock-to-out
– Optimizing for area or speed on a module-by-module basis
– Providing constraint-driven optimization (Synopsys, Exemplar, and XST)
Xilinx-Specific Code
Separate Xilinx-specific code and instantiations from the generic
HDL
– Allows easier migration to other technologies
At the top-level, create a Xilinx “wrapper” to instantiate SelectIO
interface buffers or DCMs
– As well as any other top-level, Xilinx-specific instantiations
• BUFGs (global clock buffers)
• Block RAMs
• Cores (optimized components from the Core Generator tool)
At the sub-block level, create Xilinx-specific hierarchical blocks
for Xilinx-specific code
Xilinx-Specific Hierarchy
Code Conversion Steps
A ten-step guide to design conversion
– Step 1: Convert memories (using the Core Generator tool)
– Step 2: Convert DCMs and PLLs (using the Architecture Wizard)
– Step 3: Convert SERDES (using the ChipSync Wizard)
– Step 4: Convert DSP (using the Core Generator tool)
– Step 5: Replace IP (using the Core Generator tool)
– Step 6: Use the Xilinx SRL (HDL)
– Step 7: Use clock enables (HDL)
– Step 8: Employ other good HDL coding styles (HDL)
– Step 9: Pipeline combinatorial logic (good design practice)
– Step 10: Build effective finite state machines (HDL)
Replace ASIC Memory
Depth, width, and functionality will determine the type of memory
to use
– Off-chip RAM
• Megabytes of memory storage
• Use SelectIO interfaces, DCM, and PLL for high-performance chip to chip
– Block SelectRAM™ memory
• 36 kb each—can be expanded for larger memories
• Configurable port aspect ratios
• Single-port, FIFOs, state machines, synchronous ROM
– FIFO
• Dedicated FIFO logic
– Distributed (LUT) RAM
• Synchronous write, asynchronous read
• Depth < 32 provides fastest performance
• One read and write port; one read-only port for dual-port RAMs
Off-Chip Memory
Controllers for off-chip memory can be implemented in a Xilinx
FPGA
– Use the Memory Interface Generator (MIG)
The SelectIO technology resources allow for direct interaction
with many different memory threshold levels
– HSTL or SSTL
Several downloadable memory controllers available (VHDL and
Verilog) from the Xilinx Memory Corner
– www.xilinx.com  Technology Solutions  Memory
Block SelectRAM Memory Use
Simple dual-port and single-port synchronous RAMs can be
inferred
by Mentor, Synopsys, and XST
– Your coding style must include
• 1) Synchronous write
• 2) Registered read address
• 3) Requires synthesis attributes for
inference of proper resources
For advanced block RAM use,
create the RAM with the CORE
Generator tool
– Configurable aspect ratio, for example
• Port A – 512 x 8; Port B – 256 x 16
• Port A – 1024 x 8; Port B – 1024 x 32
Block SelectRAM Memory Inference
type blockram_512x8 is array (0 to 511)
of std_logic_vector(7 downto 0);
signal mem : blockram_512x8;
signal addr_q : std_logic_vector (8 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
addr_q <= addr;
if we = '1' then
mem(conv_integer(addr)) <= di;
end if;
end if;
end process;
do <= mem(conv_integer(addr_q));
Block RAM Inference Notes
Synthesis tools can only infer “simple” block RAMs, that is
– Single-port block RAMs with read and write on the same port
– Dual-port block RAMs with read and write on individual ports
Synthesis tools cannot infer block RAMs with
– Configurable aspect ratios
• Ports with different widths
– With output enable and reset functionality
– Block RAMs with read and write capability on both ports
– Dual-port with different clocks on each port
These limitations for inferring “advanced” block RAMs can be
overcome by creating the RAM with the CORE Generator tool or
instantiating primitives
Memory Interface Generator
Generates a complete
memory
controller and interface
design
– Output: RTL, UCF,
documentation, and timing
analysis
• VHDL or Verilog
– Choose from a predefined
catalog of available devices
and interfaces
– Checks SSO and all pin selection
rules
– Available as part of the CORE
Generator tool (free)
Distributed RAM
Distributed memory resources can be correctly inferred by
Synopsys, Mentor, and XST
– All distributed RAMs can be inferred
• Requires characterization of
 1) Synchronous write
 2) Asynchronous read
– Older Synopsys tools may infer combinatorial feedback loops
• How would you find out?
Can also be created with the CORE Generator tool
– This is generally recommended
Distributed RAM Example
reg [3:0] ram64x4 [0:63];
always @ (posedge clk)
if (we)
ram64x4[addr] <= din;
assign dout =
ram64x4[addr];
Distributed ROM
ROM can be inferred by Mentor, Synopsys, and XST
– In VHDL, create an array of constants
– In Verilog, use a case statement with the address as the selector
expression and assign constant values at those addresses
Distributed ROM Example
type rom4x2 is array (0 to 3) of
std_logic_vector (1 downto 0);
constant rom : rom4x2 := ("00", "11",
"01", "10");
begin
dout <= rom(conv_integer(addr));
Digital Clock Manager and PLL
The DCM provides powerful clock management features
– DLL is used to eliminate clock skew
– DFS is used to provide a wide range of clock synthesis
– DPS is used for fine-grain phase shifting
The PLL provides frequency synthesis and jitter filter
Replace an ASIC PLL with a Xilinx PLL (or a DCM)
– Be aware of the DCM limitations by referring to your FPGA’s data sheet or
user guide
DCM Instantiation
Instantiate the
DCM primitive,
IBUFG clock
input primitive,
and BUFG global
clock buffer primitive
IBUFG
– Assigns input signal to a
dedicated clock pin
BUFG
– Gets the chosen clock on
a global buffer
Standard CMT Configurations
Use each DCM and
PLL individually
InClk 1
DCM
InClk 2
PLL
InClk 3
DCM
DCM
InClk 1
Filter DCM
output clock
jitter
InClk 1
PLL
To Global
Clocks
CMT
To Global
Clocks
CMT
PLL
To Global
Clocks
DCM
CMT
Filter high clock jitter
before reaching the
DCM
Three Types of Clock Resources
I/O Column
Global
clocks
I/O
clocks
Clock region height:
• 20 CLBs
• 40 I/Os (1 bank)
Regional
clocks
Global
Muxes
Clock region width:
• One half the chip
8–24 clock regions per
device
Performance matched to
application needs
• 710-MHz I/O Clocks
• 550-MHz Global Clocks
• 300-MHz Regional Clocks
Virtex-5 FPGA I/O Clocking
I/O Column
Per region:
• Four clock-capable I/Os
• Four I/O clock buffers
• Four I/O clock nets
• BUFIOs cannot drive IOCLK
track in adjacent region
Clock-Capable I/O
I/O Clock Buffer (BUFIO)
I/O Clock Net (IOCLK)
Ideal for sourcesynchronous
interfaces
Virtex-5 FPGA Regional Clocking
2
2
4
Per region:
• Four clock-capable I/Os
• Two regional clock buffers
• Four regional clock nets
Clock-capable I/O
2
2
4
Regional Clock Buffer (BUFR)
Regional Clock Net (RCLK)
2
2
4
2
Easily create many clock
domains per FPGA
Architecture Wizard
Double-click Create New
Source
– Select IP (CORE Generator &
Architecture Wizard) and click
Next
Clocking Wizard
Choose function
• Optimal DCM/PLL flow
automatically selected
- or Choose component
• Program as desired
Customize the DCM
Xilinx Clocking Wizard
Main window
– Select pins
– Specify
• Reference source
• Clock frequency
• Phase shift
Use the GUI to
instantiate and
program your
clocking
components
– Advanced button
Wizard generates
ready-to-use
VHDL or Verilog
wrappers and
components
SelectIO Technology
Instantiate SERDES resources with the Memory Interface
Generator (MIG) or by direct instantiation of resources
customized with the ChipSync Wizard
Instantiate SelectIO interface buffers to connect directly to over
40 different I/O standards
– Eliminates threshold translators; therefore decreasing delay and board
area
– Synthesis tools allow the SelectIO interfaces to be specified in their
constraint tools or through code attributes
Single-ended and differential I/O standards can also be selected
in PinAhead or set in a UCF
PinAhead
Pin Assignment
analysis
– Tool includes a
DRC check and
WASSO
analysis
Allows you to
see both a
Package and
Pin view of your
design
Makes it easy to
make pin
assignments
and attributes
Properties,
Selection Views
Package View
Clock Regions View
I/O Ports View
Package Pins View
Device View
Source-Synchronous Memory
ChipSync technology
ChipSync technology
– Programmable IDELAY and ODELAY
– Integrated I/O SERDES
Fast regional and I/O clocks
Embedded ECC logic
– Reduces logic resources
– Increases performance
Proven memory interfaces
– DDR-II DRAM and QDR/QDR-II, for
example
XCITE: Internal impedance control
Data
Virtex™-5
FPGA
Forwarded
CLK/DQS
SelectIO™
interface
ISERDES
Frequency division
– Data width to 10 bits
Dynamic signal alignment
– Bit alignment
– Word
alignment
ChipSync™
Data
– Clock
alignment
– Supports
CLK
Dynamic
Phase Alignment
(DPA)
ISERDES
FPGA Fabric
CLKDIV
CLK
BUFIO
n
÷
BUFR
OSERDES
Two separate SERDES included
– Data SERDES: 2, 3, 4, 5, 6, 7, 8, 10 bits
– Three-state SERDES: 1, 2, 4 bits
• Ideal for memories
ChipSync™
n
OSERDES
CLK
m
CLKDIV
BUFIO/BUFR
DCM/PMCD
FPGA Fabric
ChipSync Wizard
Generates a complete
SERDES
interface
– Provides a VHDL or Verilog
instantiation plus a Xilinx netlist
(.xaw file extension)
– Choose from a list of supported
I/O standards and SERDES
programmability
– Available as part of the CORE
Generator tool (free)
Summary
To obtain the desired performance and area goals, the design
needs to be optimized for Xilinx FPGA flexibility
– This will require instantiating the appropriate resources with the
appropriate tool
Each synthesis tool requires different resources to be
instantiated
– Know the limitations of your synthesis tools ability to infer resources
We started the ten-step guide to design conversion
– Step 1: Convert memories (using the CORE Generator tool or MIG)
– Step 2: Convert DCMs and PLLs (using the Architecture Wizard)
– Step 3: Convert SERDES (using the ChipSync Wizard)
Where Can I Learn More?
Xilinx online documents
– www.support.xilinx.com
• Software manuals
 Synthesis and Simulation Design Guide
» Includes general recommendations for coding practices and coding
tips for specific FPGA families
• Virtex-5 FPGA User guide (SERDES, clocking resources)
Xilinx Education Services courses
– www.xilinx.com/training
• Xilinx tools and architecture courses
• Hardware description language courses
• Basic FPGA architecture and other Free Videos!
How to Convert ASIC Code to FPGA Code
Part 2
Intro to VHDL or
Intro to Verilog
3
days
FPGA and ASIC
Technology Comparison
Curriculum
Path
FPGA vs. ASIC
Design Flow
ASIC to FPGA Coding
Conversion
Virtex-5 Coding Techniques
Spartan-3 Coding Techniques
Fundamentals of
FPGA Design
Designing for
Performance
for
1
day
2
days
Advanced FPGA
Implementation
ASIC Design
2
days
Welcome
A ten-step guide to design conversion
– Step 1: Convert memories (using the CORE Generator™ tool)
– Step 2: Convert DCMs and PLLs (using the Architecture Wizard)
– Step 3: Convert SERDES (using the ChipSync Wizard)
– Step 4: Convert DSP (using the CORE Generator tool)
– Step 5: Replace IP (using the CORE Generator tool)
– Step 6: Use the Xilinx SRL (HDL)
– Step 7: Use clock enables (HDL)
– Step 8: Employ other good HDL coding styles (HDL)
– Step 9: Pipeline combinatorial logic (good design practice)
– Step 10: Build effective finite state machines (HDL)
After completing this module, you will able to:
Optimize ASIC code for implementation in an FPGA
Describe the steps to perform ASIC to FPGA code conversion
Code Conversion Steps
A ten-step guide to design conversion
– Step 1: Convert memories (using the CORE Generator™ tool)
– Step 2: Convert DCMs and PLLs (using the Architecture Wizard)
– Step 3: Convert SERDES (using the ChipSync Wizard)
– Step 4: Convert DSP (using the CORE Generator tool)
– Step 5: Replace IP (using the CORE Generator tool)
– Step 6: Use the Xilinx SRL (HDL)
– Step 7: Use clock enables (HDL)
– Step 8: Employ other good HDL coding styles (HDL)
– Step 9: Pipeline combinatorial logic (good design practice)
– Step 10: Build effective finite state machines (HDL)
IP Cores
Xilinx provides intellectual property cores for your design via
the CORE Generator tool
Use the CORE Generator tool to generate LogiCORE™ IP
– LogiCORE IP are supported by Xilinx
– Some point solution cores have a charge associated, but almost all are
FREE
Use the CORE Generator tool to find information on
AllianceCORE IP
– AllianceCORE IP are those sold through Alliance partners—third-party
vendors
– All have a charge associated
– All are supported by third-party vendors
CORE Generator Tool IP
Basic elements
– Counters, comparators, and shift registers
DSP functions
– FIR filters, correlators, modulation, transforms, trig functions, and waveform
synthesis
Math functions
– Dividers, floating point module, multipliers, MACs, and square-root
generators
Memories
– All combinations of block RAM/ROM, FIFOs, MIG, and CAMs
FPGA features
– ChipSync™ technology, Clocking Wizard, RocketIO GTP Wizard, System
Monitor, XtremeDSP slice (more math functions)
Standard bus interfaces
– PCI™, PCI-X™, PCI Express®, and Serial RapidIO technology
Core Benefits
Why use the CORE Generator tool for implementing high-level
cores?
– Cores are pre-tested and use optimum device resources
– Engineering cost and time can be reduced
– Some are Relationally Placed Macros (RPMs) providing optimized speed
and area results
– VHDL and Verilog simulation models are provided
Use the SRL
Xilinx Virtex®-based FPGAs have the ability to use a LUT as a 16
x 1 shift register (the Virtex-5 FPGA can make a 32 x 1)
– SRL is used as a pipeline delay element or to capture burst data
– Serial in and serial out
• Non-loadable
• No parallel-in/out
Saves flip-flops
– Saves resources over an
ASIC shift-register
implementation
SRL Inference
SRLs can be inferred by Synopsys, Mentor, and XST
SRLs can also be instantiated by using an SRL primitive or
through the CORE Generator tool
– Use the characterization
• 1) Synchronous shift
• 2) Asynchronous read
• 3) No set or reset functionality
Verilog:
always @ (posedge clk)
// synchronous shift
sr <= {sr[14:1], din};
// asynchronous read
dout <= sr(15);
VHDL:
process (clk)
begin
if rising_edge(clk) then
-- synchronous shift
sr <= sr(14 downto 1) &
din;
end if;
end process;
-- asynchronous read
dout <= sr(15);
SRL with Enable Inference
Likewise, the SRLE can be inferred
VHDL:
process (clk)
begin
if rising_edge(clk) then
if en = ‘1’ then
-- synchronous shift with enable
sr <= sr(14 downto 1) & din;
end if;
end if;
end process;
-- asynchronous read
dout <= sr(15);
Verilog:
always @ (posedge clk)
if (en) // synchronous shift with enable
sr <= {sr[14:1], din};
// asynchronous read
dout <= sr(15);
Enhanced Register
Virtex-5 registers provide clock enables, synchronous sets, and
synchronous resets—directly on the register
All three can be used on any register
– To directly use the pins on the register, the priority must be: Reset, Set,
CE
By having these pins directly on the register, the fan-in to the
LUT is reduced
– Without a direct pin on the register, these functions would be implemented
through the LUT before the register
Enhanced Register Example
process (clk)
begin
if rising_edge(clk) then
if reset = ‘1’ then -- synchronous reset
data <= (others => ‘0’);
elsif set = '1' then
-- synchronous set
data <= (others => '1');
elsif ce = '1' then
-- clock enable
data <= data_in;
end if;
end if;
end process;
Synchronous Design
Replace gated
clock circuits with a
CE circuit
Clock Enable Circuit
always @ (posedge clk)
begin
count <= count + 1;
-- infers a decoded clock enable
if (count == 4'b1110)
q <= d;
end // always @ (posedge clk)
Synchronous Set and Reset
For internal reset circuits, use a synchronous set or reset
Similar to the gated clock example, an asynchronous signal
that provides a set or reset can glitch, propagating erroneous
data
Synchronous Reset
Be careful with Global Resets
− Only one reset port
Synchronous Reset Example
process (clk)
begin
if rising_edge(clk) then
count <= count + 1;
if count = "1110" then -- synchronous reset
q <= (others => '0');
else
q <= d;
end if;
end if;
end process;
Inference of Arithmetic Logic
Arithmetic logic is implemented by using the dedicated carry
chain
For access to the dedicated carry chain, the HDL must use
arithmetic operators
– +, –, *, /, >, <, =
– That is, you will not infer the use of the carry chain by explicitly building the
arithmetic logic
• For example, Half_Sum <= A xor B will not infer the carry chain
• Half_Sum <= A + B will infer the carry chain
Counters
To increase performance, try different types of counters
– Binary: Slow, familiar count sequence; fewest amount of registers
– One-hot: Fast; uses the maximum number of registers
– Johnson: Ring counter; fast and uses fewer registers than one-hot
encoding
– LFSR: Fast, pseudo-random sequence and uses few registers
Decode Logic Example
Instead of this…
Use case statements for decode logic
whenever possible
process (clk)
begin
if rising_edge(clk) then
cs0 <= '0'; -- default value
cs1 <= '0'; -- default value
cs2 <= '0'; -- default value
if addr <= "0011" then
cs0 <= '1';
elsif (addr > "0011" and
addr <= "0111”) then
cs1 <= '1';
elsif addr > "0111" then
cs2 <= '1';
end if;
end if;
end process;
Best Decode Solution
…use this
Use case statements for
decode logic whenever
possible
process (clk)
begin
if rising_edge(clk) then
cs0 <= '0'; -- default value
cs1 <= '0'; -- default value
cs2 <= '0'; -- default value
case (conv_integer(addr)) is
when 0 to 3 => -- x“0000” to x”0011”
cs0 <= ‘1’;
when 4 to 7 => -- x”0100” to x”0111”
cs1 <= ‘1’;
when 8 to 15 => -- x”1000” to x”1111”
cs2 <= ‘1’;
when others => null;
end case;
end if;
end process;
High Performance
To achieve high performance in FPGAs, you may have
to add pipeline delays
– The biggest issue to consider is latency requirements
– Remember, the registers exist on the die, and the Xilinx
architecture is register rich
– Note that Virtex-5 does not need as much pipelining
You may also need to perform “retiming”
– Relocating registers to move part of a combinatorial path delay
from one side of the register to the other side
To increase chip-to-chip performance, register all inputs
and outputs of the chip
Use the DCM to eliminate clock distribution delays on
(and off) chip for decreased chip-to-chip delays
Increasing Performance
Multipliers
– Use DSP slice multipliers created in the CORE Generator tool
Register selector expressions, inputs, and outputs for
multiplexers and decoders
– Register all inputs for multiplexers
Register multiple stages of an adder
Register inputs and outputs at the top level
– Increase chip-to-chip performance
Register outputs of behavioral sub-blocks
– Synchronous design methodology
Analyze Delays
Analyze the delays on combinatorial paths to determine
whether a pipeline delay is required
– Virtex-5 should use maximum 3 logic levels
– Other devices should use maximum 4 logic levels
But you make your
own definition of
performance!
Clock Frequency Based on the Number of LUTs Between
Registers: XC2V1000 -5
400
350
Frequency
300
8 LUTs
250
6 LUTs
200
4 LUTs
150
2 LUTs
100
50
0
bad
med
good
Relative Placement of Logic
free
FSM Encoding Style
To achieve high performance for FSMs, consider choosing an
alternative encoding style
– One hot is the most popular, but best to re-synthesize large and
complex FSMs for binary and Gray as well
– FSM Performance depends on…
• LUT architecture
• Number of inputs
• Number of states
• Desired speed
• Complexity (number of transitions)
• Amount of available resources
– For very large state machines (greater than 32 states), you may want to
consider gray-encoding style
– For small state machines (fewer than four states), binary encoding will
generally provide equivalent performance
FSM Coding Style
Use case statements rather than if-then-else statements
– Logic will be implemented in parallel, reducing the longest delay path
Separate next-state logic from output decoding logic
– Place next-state decoding logic and output decoding logic in a separate
process or always block
• Prevents the synthesis tool from sharing logic resources, which generally results
in less delay but more area
Be aware of inadvertent latch or clock-enable inference
– Use default assignments before the case statement
– Clock enables are not always bad; however, be careful of lengthy
decoding logic for the clock enable
Summary
To obtain the desired performance and area goals, the design
needs to be optimized for a Xilinx FPGA
– This will require you following all of our HDL coding recommendations
Each synthesis tool requires different resources to be
instantiated
– Know the limitations of your synthesis tools ability to infer resources
Use good HDL coding styles (check out the Videos)
We finished the ten-step guide to design conversion
–
–
–
–
–
–
–
Step 4: Convert DSP (using the CORE Generator tool)
Step 5: Replace IP (using the CORE Generator tool)
Step 6: Use the Xilinx SRL (HDL)
Step 7: Use clock enables (HDL)
Step 8: Employ other good HDL coding styles (HDL)
Step 9: Pipeline combinatorial logic (good design practice)
Step 10: Build effective finite state machines (HDL)
Where Can I Learn More?
Xilinx online documents
– www.support.xilinx.com
• Software manuals
 Synthesis and Simulation Design Guide
 Core Data Sheet (accessible from the Core Generator)
» Provides feature description and resource utilization info
 Xilinx Unified Libraries Guide
Xilinx Education Services courses
– www.xilinx.com/training
•
•
•
•
Virtex-5 FPGA Coding Techniques Video (Free)
Spartan-3 FPGA Coding Techniques Video (Free)
Fundamentals of FPGA Design
Designing for Performance
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