Adaptive Data Analysis and Processing Technology (ADAPT) Reconfigurable Computers for Spacecraft Use • Adapt to changing mission requirements after launch • Reduce spacecraft resources for.
Download ReportTranscript Adaptive Data Analysis and Processing Technology (ADAPT) Reconfigurable Computers for Spacecraft Use • Adapt to changing mission requirements after launch • Reduce spacecraft resources for.
Adaptive Data Analysis and Processing Technology (ADAPT) 1 Reconfigurable Computers for Spacecraft Use • Adapt to changing mission requirements after launch • Reduce spacecraft resources for onboard storage and downlink from high data bandwidth instruments by reducing data rates from the instruments • Hardware fabrication before algorithms are completed • Update or correct algorithms after launch • Reduce engineering set up times for science observatoriesReduced setup times • FPGAs offer high performance and processing power • Physical design remains the same; easily tailor control and data interfaces • Minimizes instrument and system development time • Mitigates hardware and software errors in flight • Multiple configurations can be stored for rapid adaptations 2 AIM 1st Demonstration – Reconfigurable Computing in Space • FedSat-1 – 50 kg microsatellite, LEO ~1000 km altitude • Adaptive Instrument Module (AIM) - Precursor to ADAPT – Includes an 80C196 processor and a Xilinx XQR4062 FPGA that performs reconfigurable processing – 890 grams, dissipates < 2 W – Launched December 14, 2002 on Australian FEDSAT – AIM partners - APL, Queensland University of Technology, Goddard Spaceflight Center, and Langley Research Center 3 Challenge • Challenges for effective use in spacecraft: Configuration Memory Upsets: SRAM-based FPGAs are susceptible to radiation-induced upsets in configuration memory. The frequency of these upsets must be investigated, and techniques developed to detect and correct them. Management of Multiple Configurations: Spacecraft have limited onboard resources and limited communications to ground stations. Techniques for managing the configuration data for FPGAs onboard a spacecraft will be very different than ground applications. These techniques need to be investigated, developed and analysed. Prototype Demonstration: A prototype AIM needs to be flown as a standalone experiment on a space mission to validate the initial design decisions made and evaluate improvements in satellite performance. 4 Requirements • Implement a low cost, radiation hardened, reconfigurable processor for Fedsat-1 and other spacecraft • Use Xilinx XQR4062 FPGA as the heart of the reconfigurable processor • Store and manage multiple Xilinx FPGA configurations • Able to upload additional configurations • Detect, correct, and log single event upset induced configuration errors autonomously in the Xilinx FPGA • Run standalone reconfigurable computing experiments • Process instrument data with reconfigurable hardware • Interface to spacecraft command and data handling system • Generate voltages from spacecraft +28V bus 5 Design • The AIM consists of the following components: – A 62,000 gate SRAM-based FPGA ( Xilinx XQR-4062XL) – A 16-bit microcontroller ( UTMC UT80C196KD) – 512 kbytes of EEPROM to hold microcontroller boot and application code – 8 Mbytes of non-volatile Flash to hold configurations for the Xilinx – 1 Mbyte of SRAM for microcontroller program and data – 0.5 Mbytes of SRAM for Xilinx data processing memory – An RS422 serial port for communication with the satellite command & data handling system – An uncommitted communications port connected directly to the Xilinx, to be configured on a mission-by-mission basis. – Power converter circuitry to provide 3.3V and 5V from 28V – Voltage and Temperature status lines 6 AIM Flight Module Area Study 145 mm (5.65 in) LM193 DC/DC Conv. h = 8.38 LM185 EMI Filter h = 8.38 LT1086 Spare 9 pin Spare 4MB x 8 FLASH UTMC 80C196KD Microcontroller AC74 HC14 Actel 1280A FPGA HC14 Xilinx XQR4062XL FPGA Osc. 175 mm 512K 128K(6.83 x8 in)x 8 SRAM EEPROM 422T 9 pin 422R 4MB x 8 FLASH 128K x 8 EEPROM HC14 HC14 9 pin 25 pin Flight Unit Characteristics • Weight: estimated 1 kg • Size: 16 cm x 17.5 cm x 3.0 cm • Power: 2.5W (from +28V) • Parts selected for radiation tolerance and availability: – Xilinx XQR4062XL - 62,000 gate SRAM-based FPGA – UTMC UT80C196KD 16-bit microcontroller – SEI 28C010TRPFB-15 512Kx8 EEPROM – SEI 29F0408RP 4Mx8 Flash – Austin/Motorola 5C512K8F 512Kx8 SRAM – Actel A1280A fuse link FPGA 512K x 8 SRAM 512K x 8 SRAM 7 AIM Flight Unit Test 8 ADAPT Objectives • Develop a prototype reconfigurable processor utilizing state-of-the-art Field Programmable Gate Array technology • Develop algorithms that meet the requirements for two Earth Science Enterprise mission scenarios – Microwave Radiometers – Fourier Transform Spectrometers (FTS) • Design, fabricate, and test a flight-grade reconfigurable processor • Demonstrate algorithms using flight-grade reconfigurable processor 9 ADAPT Hardware Design - commercial standards • Xilinx Virtex II FPGA (XC2V1000) – Equivalent of 1 million gates and 720k bits of RAM – 40 Dedicated 18x18 Multipliers (300 MHz) – A wide range of IP cores are available: • DSP functions • Processors • Math functions • New designs can be implemented with a wide range of development tools 10 ADAPT - Hardware Definition • • • ADAPT stores multiple FPGA configurations in flash memory. Instrument processing algorithms can be changed in real time. – Fuse-programmed Actel FPGA implements the system interface – Host processor chooses configurations for the Xilinx Virtex II FPGA. Operation: – – – • • • • Xilinx FPGA connects to external SRAM memory to store intermediate results, coefficients, and variables Voltage regulators supply the low-voltage Backplane supplies standard +3.3 and +5V power Xilinx clock may derive from: – – – • • Host selects configuration Second Actel FPGA reads back and verifies configuration of Xilinx FPGA Automatically corrects the configuration and notifies the host processor when it detects discrepancies. on-board oscillator the PCI bus clock or from the I/O connector Xilinx FPGA on-chip temperature sensor routes to I/O connector. Instrument data flow through: – – PCI bus I/O connector 11 ADAPT Board Block Diagram Oscillator Front Panel I/O Connector (Instrument Data) SRAM Voltage Regulators J2 I/O Connector on back-plane (Instrument Data) Xilinx Virtex II FPGA (XC2V1000) Flash Memory Actel Supervisor (Configuration/ Readback) PCI Bus Power Actel Host interface PCI Bus (Host Processor Communications) 12 ADAPT Breadboard Instrument Interface, 192-pin connector 128Kx32 SRAM FLASH Memory Holds multiple Xilinx FPGA configurations Xilinx Virtex-II Million-gate FPGA CompactPCI J2 Connector provides additional I/O capability CompactPCI J1 Connector for Host interface Supervisor FPGA (Actel A54SX32) performs continuous Xilinx configuration checking Host FPGA (Actel A54SX32) implements 32-bit CompactPCI interface 13 ADAPT Configuration Manager • Implemented in Actel 54SX32 radiation hardened FPGA – Hardware Triple-Voted S-Modules • Runs at 50MHz • VHDL Design – modeled after C program which was initially used to verify the config/readback scheme 14 ADAPT Configuration Manager Flash Memory Interface Data to PCI Actel State Machine Commands from PCI Actel Xilinx SelectMap Interface 15 ADAPT Configuration Manager Modes If all goes well START(IDLE) Xilinx configuration UPLOAD Xilinx Continuous Frame-wise readback error On Command Through PCI Host Actel Configuration occurs frame by frame As opposed to normal Xilinx Upload This allows data structure stored in Memory to be the same for readback / SEU correction. During frame-by-frame readback, Contents of each frame are compared With contents of rad-hard Flash. (Mask and config bits are interleaved) 16 ADAPT Configuration Manager Modes Put Xilinx back into write mode Write Corrected Frame, Pad Pipeline Switch Xilinx back to read Mode Signal PCI Host Interface which makes IRQ Xilinx Active Partial Reconfiguration is used, new configuration frame is uploaded while the device is operating. Xilinx experiences no operation interruption Manager continues reading where it left off before encountering SEU Times : Programming : 100 ms Roundtrip Readback : 200 ms 17 ADAPT Host Interface FPGA • Implemented in Actel 54SX32 • Uses Actel IP : PCI Core v 5.2.1 – APL is targetting this core for other space missions – some corrections incorporated • bug fixes • workarounds for Actel timing hazards as they are discovered. • 33 MHz, 32-bit PCI Target Only 18 ADAPT Host Interface FPGA Flash Control / Data To 3V Compact PCI Backplane PCI Interface To Config Manager Config Manager Control / Status Write - Fifo To Xilinx Interrupt (currently Associated with SEU Detection) From Xilinx Read - Fifo 19 under development ADAPT Usage Flow + Software • Design Xilinx using ISE Foundation Toolset – Use Rad-tolerant techniques to protect RAM and flipflops • Use ADAPT compiler and linker to generate files suitable for residing in flash memory • Use ADAPT flash-software to program flash from flashfile. • Send command through PCI interface to start (configure) Xilinx with a particular config from flash. – If option is enabled, SEU mitigation will proceed immediately upon successful configuration – Status of configuration / readback process can be read through software driver. 20 Upcoming Test / Refinements • Testing of Host Interface FIFOs to allow Xilinx to send data via PCI if desired • Make slight modification to Compiler / Linker to store multiple configurations in Flash • Packaging Software into a more user-friendly installation package • Simulation of SEU in Xilinx FPGA • Environmental tests • Radiation tests 21 Example of ADAPT Instrument – onboard data storage – downlink bandwidth • Generic design can be used for different instruments Instrument Sensor Front End Electronics 3U Compact PCI Backplane • ADAPT will implement real time data reduction, compression, and feature extraction algorithms. • Minimizes spacecraft resources ADAPT Instrument Processor Spacecraft C&DH Interface Spacecraft Interface Spacecraft Power DC/DC Converters 22 Microwave Radiometer Digital I & Q 1/64 Z11,-1,1,-1,… -5/64 Z120/64 Σ Z1- Digitized Radiometer Signal (6-bit data) QX 20/64 Demultiplexer Z1-5/64 Z11/64 -1,1,-1,1,… Z1- 64 MHz data rate Z1- Z1- 32 MHz data rate -32/64 IX 23 Microwave Radiometer Digital Correlator ADAPT BOARD MAC Ch 1, 6-bit data I1 Digital I & Q Ch 2, 6-bit data Q1 I2 Digital I & Q Q2 I1xI1 I1xQ2 Q1xQ1 Q1xI2 I2xI2 I2xI1 Q2xQ2 Q2xQ1 Parallel-toSerial Converter/ Multiplexer Serial Output (0.1 sec Integration Period) 24 Microwave Radiometer Interface Hardware LVDS Receiver Box ADAPT Hardware Radiometer Interface Box 25 FTS Motion Control Application VHDL-coded 16-bit Motion Controller for Fourier Transform Spectrometers 26 FTS System GSE & Data Collection ADC 18-bits IR Detector Laser Detector SampleOffset Velocity* ( ) Motion Control IR Velocity Spectral Resolution (~0.25 cm-1) 27 Control Configuration CNTin + PID (COMPENSATOR) Electronics HW VHDL CNTfbk Decode Motion Control 28 & Compensator 40 PID 16 TCtoMO (-) 20 CLAMP 20 21 CLAMP CNTfbk 20 Latch CNTin 16 DAC Tc DAC ( K E ) ( K E ) [ K ( E E )] P IN I I D IN P 29 Electronics Vdd Vdd 2 Vdd C3 10U Vdd C6 0.01u R135k C1 10u R5 10k 7 3 7 3 + 0 V+ U1 OUT R2 1.5k 0 6 2 - 418 OP-27/AD V-N1N2 - 418 OP-27/AD V-N1N2 R3 10k 0 V+ U2 OUT R6 10k 6 2 Voffset + 0 4 3 + 2 1N4742 Vdd 2 Rl+ V+ CL+0.64 1 ToMotor PA07/AM OUT 7 BAL 5 - 6 8 RlV- CL-0.64 D2 D1 1 2 R4 10k R1210k U4 1 C2 10u 0 R8 =1k C3 10u C8 0.01u Vee 0 Vee C4 10U 0 C4 10u 10K POT D4 1N4376 Rs 175k R1110k 1 1N4742 D3 1N4376 2 C1 0.1U C5 0.01u R1 1.1k 1 0 Vee C2 0.1U Vee C7 0.01u Vee 30 Resource Utilization for Xilinx Virtex-II Million Gate Device • Number of Slices: 324 out of 5,120 – 6% • Number of Flip Flops: 182 out of 10,240 – 1% • Number of LUTs: 592 out of 10,240 – 5% RMS Velocity Error 31 Use of ADAPT Technology in IIP 3U CompactPCI Chassis Stepper Motor for Scene Selection Mirror HRE Etalon PZT Control HRE Etalon Control Electronics 4-Axis Controller LRE Etalon Control Electronics 4-Axis Controller CompactPCI Bus Capacitive Sensor Feedback LRE Etalon PZT Control 1.26 GHz PXI Embedded Controller Capacitive Sensor Feedback FPA Analog Inputs (Housekeeping Parameters) Readout Integrated Circuit Pixel Binning and Frame Averaging Electronics Analog Interface Electronics 16-Channel A/D 73 GB Rugged Removable Hard Drive SCSI Interface Real-Time Display/ User Interface Computer Ethernet Interface IDE Interface Solid State Disk (OS, Program files, etc.) GPS Interface 32 Yellow = Performed by ADAPT hardware Green = Could be performed with ADAPT hardware Accomplishments • • • • • • • Developed a simplified technique for partial-reconfiguration (SEU correction) Efficient format for storing configuration/readback data in flash memory developed (3 x reduction in memory over standard bitstream format) Convert Xilinx bitstream files to ADAPT formatFabricated ADAPT board Completed design/assembly/test of test-adapter board that allows software driven testing of Xilinx configuration interface Demonstrated configuration / active readback / partial active reconfiguration (correction) Host Actel designed and tested Developed Host Software: – Linux Device Driver – Bitfile Compiler / linker – Flash erase / program / verify – Configuration Loader Demonstrated upload,readback, partial reconfiguration under Actel control 33