Transcript Target electronics and DAQ

MICE
Electronics & DAQ
P J Smith
University of Sheffield
MICE
Overview
The target controller upgrade is a 3 phase project to upgrade and integrate target
control electronics:
Phase 1 – Move the control algorithms into an FPGA and interface the FPGA board
to the older style IO cards. To place the FPGA under computer control to give a
much improved user interface.
The Phase 1 controller is currently operational in R78.
Phase 2 – To improve the design of the older IO cards, giving them more
functionality and placing the entire target control system onto PCBs.
Phase 3 – This is to integrate the target DAQ into the target controller.
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Phase 2 Progress
Another 3U unit to sit on here
DC1
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FPGA
DC2
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Phase 2 Progress
Work to be done is mostly testing...
Communication with FPGA has been proven.
Most digital IO has been tested
Communication with analogue components over SPI – untested.
I am adding some ‘engineering’ menus to the terminal application. This will
permit the unit to be tested/diagnosed more thoroughly. The addition of these
menus requires some more VHDL coding to be done for the FPGA.
I then intend to run some short tests of the system on an old target at Sheffield
before moving the phase 2 controller to R78.
Software
The software GUI needs updating to take account of improvements and
functionality in the controller – This work is being undertaken by Matt Robinson.
Timescale...
I expect the system will be ready for moving to RAL by early June if all goes well.
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Phase 2 Progress
Screenshot of Terminal Application
Engineering Options permit diagnostics to be
performed and give access to functionality that
would normally be hidden from the user.
There will be about ~20 Engineering options by
the time the application is complete.
The software GUI is currently being updated to
reflect the system changes. The engineering
options will be password protected.
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Installation
We would like to spend some time running the Phase 2 controller in R78 to prove the
reliability of the controller and to calibrate the BPS system. This will allow us to
ensure that the BPS system limits can be set in such a manner that they will not
trip during normal operation.
During this testing period it may be possible to move the phase 1 controller into the
MLCR. The phase 1 controller is now well tried and tested and will give a much
improved interface for MICE users during the summer run (Note that the Phase 1
controller does not have a BPS system.)
After further testing of the Phase 2 controller in R78 it will then be ready for
integrating into the MLCR. It should be relatively easy to swap the phase 1
controller out for the phase 2 controller.
As we intend to build 3 identical versions of this phase 2 controller it will then be
possible to have 2 identical systems running in R78/MLCR and a complete spare
that will be used for development work at Sheffield.
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Schedule
Additional time to code &
evaluate additional functions
required.
Additional Testing in R78 is
needed– Aim to start in early
June in R78.
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Phase 3
Phase 3 is the final part of the project and will integrate the MICE DAQ into the
target controller.
We’re starting to think about the details of how we integrate the DAQ into the
controller. It is apparent that it will be necessary to change from a USB interface to
Ethernet due to bandwidth requirements.
This will require a second FPGA board that is different to the one that is being
used to control the target– Ed is starting to consider some of these issues.
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END
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