Transcript Basic Logic Gates - Oakland University

Exam2 Review
Part 2 of Course
Digital Logic
Positional Notation
N = P4P3P2P1P0
= P4b4 + P3b3 + P2b2 + P1b1 + P0b0
Binary
101102 = 1 x 24 + 0 x 23 + 1 x 22 + 1 x 21 + 0 x 20
= 16 + 0 + 4 + 2 + 0
= 2210
Positional Notation
N = P4P3P2P1P0
= P4b4 + P3b3 + P2b2 + P1b1 + P0b0
Hex
3AF16 = 3 x 162 + A x 161 + F x 160
= 3 x 256 + 10 x 16 + 15 x 1
= 768 + 160 + 15
= 94310
Binary
Hex
0110 1010 1000
6
A
8
1111 0101 1100
F
5
C
Finding 2’s Complement
Complement
remaining bits
0 1 0 1 1 0 0 0
1 0 1 0 1 00 0
2’s complement
Copy all bits
to first 1
Negative Number
Take 2’s Complement
7510 = 4B16 = 01001011
-7510 = B516 = 10110101
FF
-4B
B4
+1
B5
Table 2.2
Positive and Negative Binary Numbers
Signed decimal
-128
-127
-126
…
…
…
-3
-2
-1
0
1
2
3
…
…
125
126
127
Hex
80
81
82
…
…
…
FD
FE
FF
00
01
02
03
…
…
7D
7E
7F
Binary
10000000
10000001
10000010
…
…
…
11111101
11111110
11111111
00000000
00000001
00000010
00000011
…
…
…
01111101
01111110
01111111
Unsigned decimal
128
129
130
…
…
…
253
254
255
0
1
2
3
…
…
…
125
126
127
Basic Gates
•
•
•
•
•
•
•
NOT Gate
AND Gate
OR Gate
XOR Gate
NAND Gate
NOR Gate
XNOR Gate
Basic Gates
NOT
X
Y
AND
X
Y
OR
X
Y
Y = ~X
not(Y,X)
Z = X & Y
and(Z,X,Y)
Z
Z
Z = X | Y
or(Z,X,Y)
X
0
1
Y
1
0
X
0
0
1
1
Y
0
1
0
1
Z
0
0
0
1
X
0
0
1
1
Y
0
1
0
1
Z
0
1
1
1
Any logic circuit can be created using only these three gates
NOT Gate
X
~X
X
0
1
~~X = X
~X
1
0
~~X
0
1
Behavior:
The output of a NOT gate is the inverse (one’s complement) of the input
AND Gate
X[1]
X[2]
AND
Z
X[n]
Behavior:
The output of an AND gate is HIGH only if all inputs are HIGH
assign Z = X[1] & X[2] & ... & X[n];
assign Z = &X;
and(Z,X[1],X[2],...,X[n]);
OR Gate
X[1]
X[2]
OR
Z
X[n]
Behavior:
The output of an OR gate is LOW only if all inputs are LOW
assign Z = X[1] | X[2] | ... | X[n];
assign Z = |X;
or(Z,X[1],X[2],...,X[n]);
Exclusive-OR (XOR) Gate
X[1]
X[2]
XOR
Z
X[n]
Behavior:
The output of an XOR gate is HIGH
only if the number of HIGH inputs is ODD
assign Z = X[1] ^ X[2] ^ ... ^ X[n];
assign Z = ^X;
xor(Z,X[1],X[2],...,X[n]);
2-Input XOR Gate
XOR
X
Y
X
0
0
1
1
Z
Z = X ^ Y
xor(Z,X,Y)
Y
0
1
0
1
Z
0
1
1
0
Note:
if Y = 0, Z = X
if Y = 1, Z = ~X
Therefore, an XOR gate can be used
as a controlled inverter
Exclusive-NOR Gate
XNOR (NOT – XOR)
X[1]
X[2]
XNOR
Z
X[n]
Behavior:
The output of an XNOR gate is HIGH
only if the number of HIGH inputs is EVEN
assign Z = ~(X[1] ^ X[2] ^ ... ^ X[n]);
assign Z = ~^X;
xnor(Z,X[1],X[2],...,X[n]);
2-Input XNOR Gate
XNOR
X
Y
Z
Z = ~(X ^ Y)
Z = X ~^ Y
xnor(Z,X,Y)
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
1
Note: Z = 1 if X = Y
Therefore, an XNOR gate can be used
as an equality detector
NAND Gate (NOT-AND)
X[1]
X[2]
NAND
Z
X[n]
Behavior:
The output of an NAND gate is LOW only if all inputs are HIGH
assign Z = ~(X[1] & X[2] & ... & X[n]);
assign Z = ~&X;
nand(Z,X[1],X[2],...,X[n]);
NOR Gate (NOT – OR)
X[1]
X[2]
NOR
Z
X[n]
Behavior:
The output of an NOR gate is HIGH only if all inputs are LOW
assign Z = ~(X[1] | X[2] | ... | X[n]);
assign Z = ~|X;
nor(Z,X[1],X[2],...,X[n]);
module gates ( X ,Z, Y );
Gates4.v
input [4:1] X ;
wire [4:1] X ;
output [6:1]
wire [6:1] Z
output [6:1]
wire [6:1] Y
Z ;
;
Y ;
;
and(Z[6],X[1],X[2],X[3],X[4]);
nand(Z[5],X[1],X[2],X[3],X[4]);
or(Z[4],X[1],X[2],X[3],X[4]);
nor(Z[3],X[1],X[2],X[3],X[4]);
xor(Z[2],X[1],X[2],X[3],X[4]);
xnor(Z[1],X[1],X[2],X[3],X[4]);
assign
assign
assign
assign
assign
assign
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
endmodule
=
=
=
=
=
=
&X;
~&X;
|X;
~|X;
^X;
~^X;
Verilog gate level primitives
Verilog reduction operators
and(Z[6],X[1],...
nand(Z[5],X[1], ..
or(Z[4],X[1], ...
nor(Z[3],X[1], ...
xor(Z[2],X[1], ...
xnor(Z[1],X[1], ..
assign
assign
assign
assign
assign
assign
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
=
=
=
=
=
=
&X;
~&X;
|X;
~|X;
^X;
~^X;
NAND Gate
X
Z
=
Y
Y
Z = ~(X & Y)
X
0
0
1
1
Z
X
Y
0
1
0
1
W
0
0
0
1
Z
1
1
1
0
Z = ~X | ~Y
X
0
0
1
1
Y ~X ~Y
0 1 1
1 1 0
0 0 1
1 0 0
Z
1
1
1
0
De Morgan’s Theorem-1
~(X & Y) = ~X | ~Y
NOT all variables
• Change & to | and | to &
• NOT the result
•
NOR Gate
X
X
Z
Y
Z
Y
Z = ~(X | Y)
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
0
Z = ~X & ~Y
X
0
0
1
1
Y ~X ~Y
0 1 1
1 1 0
0 0 1
1 0 0
Z
1
0
0
0
De Morgan’s Theorem-2
~(X | Y) = ~X & ~Y
NOT all variables
• Change & to | and | to &
• NOT the result
•
Sum of Products Design
X
0
0
1
1
Y
0
1
0
1
minterms
m0 = ~X & ~Y
m1 = ~X & Y
m2 = X & ~Y
m3 = X & Y
Sum of Products Design
Design an XOR gate
X
0
0
1
1
Y
0
1
0
1
Z
0
1
1
0
m1 = ~X & Y
m2 = X & ~Y
Z = m1 | m2
= (~X & Y) | (X & ~Y)
Product of Sums Design
X
0
0
1
1
Y
0
1
0
1
minterms
m0 = ~X & ~Y
m1 = ~X & Y
m2 = X & ~Y
m3 = X & Y
M0
M1
M2
M3
maxterms
= ~m0 = X | Y
= ~m1 = X | ~Y
= ~m2 = ~X | Y
= ~m3 = ~X | ~Y
Product of Sums Design
Design an XOR gate
X
0
0
1
1
Y
0
1
0
1
Z
0
1
1
0
M0 = X | Y
M3 = ~X | ~Y
Z = M0 & M3
= (X | Y) & (~X | ~Y)
Venn Diagrams
~X & Y
X
Y
Unity
~X & Y
X & Y
X
Y
(X & Y) | (~X & Y) = Y
Dual:
(X | Y) & (~X | Y) = Y
Absorption-1
X & Y
X
Y
Y | (X & Y) = Y
Dual:
Y & (X | Y) = Y
Absorption-2
~X & Y
X
Y
X | (~X & Y) = X | Y
Dual:
X & (~X | Y) = X & Y
Distributive Law - a
X
Y
Z
X | (Y & Z) = (X | Y) & (X | Z)
Distributive Law - b
X
Y
Z
X & (Y | Z) = (X & Y) | (X & Z)
Venn Diagrams and Minterms
X
Y
XYZ
XYZ
XYZ
XYZ
XY Z
XY Z
X YZ
Z
Venn Diagrams and Minterms
X
Y
XYZ
XYZ
XYZ
XYZ
XY Z
XY Z
X YZ
Z
XYZ + XYZ + XYZ = XZ + XY
Three-variable K-Maps
YZ
00
X
0
0
1
4
1
01
11
10
1
3
2
5
7
6
1
1
1
F = m0 | m2 | m5 | m7
= S(0,2,5,7)
Three-variable K-Maps
YZ
X
0
1
00
01
11
1
10
1
1
1
F = X & Z
| ~X & ~Z
Three-variable K-Maps
YZ
X
00
01
11
10
0
1
1
1
1
1
1
1
F = Y
| ~Z
Four-variable K-Maps
YZ
WX 00
00
01
11
10
01
11
10
0
1
3
2
4
5
7
6
12
13
15
14
8
9
11
10
F(W,X,Y,Z) = S(2,4,5,6,7,9,13,14,15)
Four-variable K-Maps
YZ
WX 00
01
11
00
01
10
1
1
1
1
1
11
1
1
1
10
1
F =
|
|
|
~W & X
X & Y
~W & Y & ~Z
W & ~Y & Z
Four-variable K-Maps
YZ
WX 00
00
1
01
11
10
01
11
1
1
1
1
1
1
10
1
F = ~W & Z
| W & X & Y
| ~X & ~Z
1
1
A 1-Bit Comparator
xi
Gin
Ein
yi
comp1bit
Gout
Eout
The variable Gout is 1 if Gin = 1 or if Ein = 1 and x > y.
The variable Eout is 1 if Ein = 1 and x = y.
Gout = Gin | Ein & x & ~y
Eout = Ein & ~x & ~y | Ein & x & y
= Ein & (~x & ~y | x & y)
= Ein & (x ~^ y)
module comp4 ( x, y, gt, eq, lt );
input [3:0] x ;
wire [3:0] x ;
input [3:0] y ;
wire [3:0] y ;
A 4-Bit Comparator
output lt ;
wire lt ;
output gt ;
wire gt ;
output eq ;
wire eq ;
x3
Gin=0
y3
G4
x2
E4
1 1 0 1
1 0 1 1
y2
x1
0
1
G3
G2
comp1bit
U3
Ein=1
x
y
comp1bit
U2
E3
1
y1
x0
1
0
1
G1
comp1bit
U1
E2
y0
G0
gt
comp1bit
U0
E1
0
eq
E0
0
lt
Turning on an LED
No current
no light
+5V
R
LED
+5V
PLD output pin
1
light
Current
+1.7V
+5V
R
R=
voltage
current
+0.2V
LED
=
0
5 - 1.7
15 x 10
-3
PLD output pin
= 220 ohms
Turning on an LED
No Current
0
CPLD output pin
0V
no light
0V
R
LED
Current
light
1
CPLD output pin
+3.2 V
R=
voltage
current
=
R
3.2 - 1.9
4 x 10^-3
0V
+1.9 V
LED
= 325 ohms
R = 330 ohms
This is what
we use in Lab
7-Segment Display
+5V
a
Common
Anode
f
b
g
e
c
d
a
b
c
d
e
f
g
a
b
c
d
e
f
g
Common
Cathode
7-Segment Display
D(3:0)
Truth table
D
0
1
2
3
4
5
6
7
a
1
0
1
1
0
1
1
1
b
1
1
1
1
1
0
0
1
c
1
1
0
1
1
1
1
1
d
1
0
1
1
0
1
1
0
e
1
0
1
0
0
0
1
0
f
1
0
0
0
1
1
1
0
g
0
0
1
1
1
1
1
0
D
8
9
A
b
C
d
E
F
a
1
1
1
0
1
0
1
1
b
1
1
1
0
0
1
0
0
c
1
1
1
1
0
1
0
0
d
1
1
0
1
1
1
1
0
seg7dec
e
1
0
1
1
1
1
1
1
f
1
1
1
1
1
0
1
1
g
1
1
1
1
0
1
1
1
AtoG(6:0)
module hex7seg(D,AtoG);
input [3:0] D;
output [6:0] AtoG;
reg [6:0] AtoG;
always @(D)
case(D)
0:
1:
2:
3:
4:
5:
6:
7:
8:
9:
'hA:
'hb:
'hC:
'hd:
'hE:
'hF:
default:
endcase
endmodule
hex7seg.v
Verilog
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
7'b1111110;
7'b0110000;
7'b1101101;
7'b1111001;
7'b0110011;
7'b1011011;
7'b1011111;
7'b1110000;
7'b1111111;
7'b1111011;
7'b1110111;
7'b0011111;
7'b1001110;
7'b0111101;
7'b1001111;
7'b1000111;
7'b1111110;
a
f
b
g
e
c
d
// 0
Verilog
SW7seg.v
// Title
// Author
: Toggle switches to 7-Segment Display
: R. E. Haskell
module SW7seg(SW,LEDR,AtoG,AAtoGG);
input [7:0] SW;
SW(7..4)
output [7:0]LEDR;
output [6:0] AtoG;
output [6:0] AAtoGG;
wire [6:0] AtoG;
wire [6:0] AAtoGG;
wire [7:0] LEDR;
AAtoGG
d7L
hex7seg
AtoG
SW(3..0)
d7R
hex7seg
assign LEDR = SW;
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
endmodule
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
Wiring up the top-level design in Verilog
AAtoGG
SW(7..4)
D(3..0)
hex7seg
d7L
hex7seg
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
= AtoG
AtoG
SW(3..0)
d7R
[a,b,c,d,e,f,g]
hex7seg
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
Wiring up the top-level design in Verilog
AAtoGG
SW(7..4)
D(3..0)
hex7seg
d7L
hex7seg
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
= AtoG
AtoG
SW(3..0)
d7R
[a,b,c,d,e,f,g]
hex7seg
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A multiplexer is a
digital switch
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0 1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Problem
How would you make a
Quad 2-to-1 MUX?
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
s
Y
0
1
A
B
mux.v
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
always @(A,B,s)
if(s == 0)
Y = A;
else
Y = B;
endmodule
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
always @(A,B,s)
if(s == 0)
Y = A;
else
Y = B;
endmodule
~S-~R Latch
1 ~S
Q 0
~Q 1
1 ~R
X
0
0
1
1
Y nand
0 1
1 1
0 1
1 0
~S
0
0
1
1
~R
0
1
0
1
Q ~Q
1
1
0
0
1
Q0
1 Disallowed
0 Set
1 Reset
1 Store
0
!Q0
To close or lock with or
as if with a latch, To
catch or fasten
S-R Latch
module RSlatchNOR ( Q ,R ,S );
input R ;
wire R ;
input S ;
wire S ;
output Q ;
wire Q ;
wire F1, F2;
R
F1
S
F2
nor #10 (F1,F2,R);
nor #10 (F2,F1,S);
assign Q = F1;
endmodule
10ns propagation delay
Q
R
S
F1
F2
Q
R
0
0
1
1
S
0
1
0
1
Q
Q0
1
0
0
store
set
reset
disallowed
D Latch
S
D
~S
Q
CLK
~Q
R
D CLK Q ~Q
0 1 0 1
1 1 1 0
X 0 Q0 ~Q0
~R
Note that Q follows D
when the clock in high,
and is latched when the
clock goes to zero.
D Latch
module Dlatch ( Q ,EN ,D );
input EN ;
wire EN ;
input D ;
wire D ;
D
Q
D Latch
EN
output Q ;
reg Q ;
always @(D or EN)
if(EN == 1)
Q = D;
endmodule
Q follows D when EN is high, and
remains unchanged when EN is low.
D Latch
D Flip-Flop
D clk Q !Q
0
0 1
1
1 0
X 0 Q0 !Q0
Q
D
clk
!Q
Positive edge triggered
D gets latched to Q on the rising edge of the clock.
Behavior
always @(posedge clk)
Q <= D;
module DFFclr (D, clk, clr, Q, notQ );
input clk ;
wire clk ;
input clr ;
wire clr ;
input D ;
wire D ;
clk
always @(posedge clk or posedge clr)
if(clr == 1)
Q <= 0;
else
Q <= D;
assign notQ = ~Q;
endmodule
Q
D
output Q ;
reg Q ;
output notQ ;
wire notQ ;
DFFclr.v
!Q
clr
Asynchronous clear
D Flip-Flop with Asynchronous Clear
A 1-Bit Register
LOAD
D
INP0
Q0
Q
CLK
~Q
~Q0
CLK
Q0next = Q0 & ~LOAD | INP0 & LOAD
LOAD
INP0
CLK
reg1
Q0
~Q0
A 1-Bit Register
LOAD
INP0
CLK
reg1
Q0
~Q0
If LOAD = 1, then INP0 gets latched to Q0 on
the rising edge of the clock, CLK
A 4-Bit Register
CLK
reg1
INP0
LOAD
INP0
CLK
reg1
Q0
~Q0
INP1
reg1
INP2
reg1
INP3
reg1
LOAD
Q0
~Q0
Q1
~Q1
Q2
~Q2
Q3
~Q3
Implementing Registers in Verilog
//
A 4-bit register with asynchronous clear and load
module reg4(Clk,Clear,Load,D,Q);
input [3:0] D;
input Clk,Clear,Load;
output [3:0] Q;
reg [3:0] Q;
always @(posedge Clk or posedge Clear)
if(Clear == 1)
Q <= 0;
D(3:0)
else if(Load)
Q <= D;
endmodule
Reg
Load
Q(3:0)
Clear
Clk
4-Bit Shift Register
data_in
Q3
D
CLK
CLK
Q
!Q
Q2
D
CLK
Q
!Q
Q1
D
CLK
Q
!Q
Q0
D
CLK
Q
!Q
shift4.v
module ShiftReg(clk,clr,data_in,Q);
input clk;
input clr;
Q3
input data_in; data_in
output [3:0] Q;
D
CLK
Q
!Q
Q2
D
CLK
Q
!Q
Q1
D
CLK
Q
!Q
Q0
D
CLK
CLK
reg [3:0] Q;
//
4-bit Shift Register
always @(posedge clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
Note non-blocking assignment
else
begin
Q[3] <= data_in;
Q[2:0] <= Q[3:1];
end
end
endmodule
Q
!Q
shift4 simulation
Ring Counter
Q3
D
CLK
CLK
Q
!Q
Q2
D
CLK
Q
!Q
Q1
D
CLK
Q
!Q
Q0
D
CLK
Q
!Q
ring4.v
module ring4(clk,clr,Q);
input clk;
input clr;
output [3:0] Q;
reg [3:0] Q;
//
4-bit Ring Counter
always @(posedge clk or posedge clr)
begin
if(clr == 1)
Q <= 1;
else
begin
Q[3] <= Q[0];
Q[2:0] <= Q[3:1];
end
end
endmodule
ring4 simulation
Johnson Counter
module johnson4(clk,clr,Q);
input clk;
input clr;
output [3:0] Q;
johnson4.v
reg [3:0] Q;
//
4-bit Johnson Counter
always @(posedge clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
begin
Q[3] <= ~Q[0];
Q[2:0] <= Q[3:1];
end
end
endmodule
Johnson Counter
3-Bit Counter
clr
count3
Q(2 downto 0)
clk
Behavior
always @(posedge clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
Q <= Q + 1;
end
module counter3 (clk, clr, Q );
counter3.v
input clr ;
wire clr ;
input clk ;
wire clk ;
output [2:0] Q ;
reg [2:0] Q ;
//
3-bit counter
always @(posedge clk or posedge clr)
begin
Asynchronous clear
if(clr == 1)
Q <= 0;
else
Q <= Q + 1;
end
Output count increments
endmodule
on rising edge of clk
counter3 Simulation
A Random Number Generator
D
Q
CLK ~Q
CLK
Q3
D
Q
CLK ~Q
Q2
D
Q
CLK ~Q
Q1
D
Q
CLK ~Q
Q0
D
Q
Q3
CLK ~Q
D
Q
Q2
CLK ~Q
D
Q
Q1
D
CLK ~Q
Q
CLK ~Q
CLK
Q3 Q2 Q1 Q0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
Q3 Q2 Q1 Q0
1
8
C
E
F
7
B
5
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
A
D
6
3
9
4
2
1
Q0
Recall Divide-by-8 Counter
Present state
State Q2 Q1 Q0
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Next state
D2 D1 D0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
D0
D
D
Q
Q
Q0
CLK ~Q
CLK ~Q
D1
D
D
Q
Q
Q1
CLK ~Q
CLK ~Q
D2
D
D
Q
Q
Q2
CLK ~Q
CLK ~Q
Use Q2, Q1, Q0 as inputs to a combinational circuit
to produce an arbitrary waveform.
Example
State Q2 Q1 Q0
s0
s1
s2
s3
s4
s5
s6
s7
0
0
0
0
1
1
1
1
1 1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
D2 D1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0 1 0
D0
1
0
1
0
1
0
1
0
y
1
1
0
0
0
1
0
1
1 1 1
Q1 Q0
00
Q2
0
1
1
01
11
10
1
1
1
y = ~Q2 & ~Q1
| Q2 & Q0
0 0 0 1 0
1
Sequence Detectors
0
0
s0
0
1
1
1
s1
0
1
s2
0
s3
0
0
1
s4
s4
1
0
Moore machine:
Output is a function
of only the state
-- 5 states
0
output
1/1
0/0
1/0
0/0
s0
s1
1/0
1/0
0/0
s2
0/0
s3
Mealy machine:
Output is a function
of the state and the
input
-- 4 states
Mealy Machine
State Register
clear
s(t+1)
C1
Next
state
x(t)
Present
input
Note: Output changes
when input changes
s(t)
Present
state
C2
z(t)
Present
output
clk
1/1
0/0
1/0
0/0
s0
s1
1/0
1/0
0/0
s2
0/0
s3
Mealy Machine
State Register
clear
s(t+1)
C1
x(t)
Present
input
Next
state
s(t)
Present
state
C2
Present
output
D
CLK
Q
z(t)
!Q
clk
1/1
0/0
1/0
0/0
s0
s1
1/0
1/0
0/0
s2
0/0
s3