Transcript Logic Design Review – 2 Basic Combinational Circuits Lecture L14.2 Verilog

Logic Design Review – 2
Basic Combinational Circuits
Lecture L14.2
Verilog
Basic Combinational Circuits
•
•
•
•
•
•
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
– Gray Code Converter
– Binary-to-BCD Converter
Combinational Logic
inputs
Combinational
Logic
outputs
Outputs depend only on the current inputs
Multiplexers
A multiplexer is a digital switch
2n
inputs
X(0, 2n -1)
MUX
n control lines
s( 0, n-1)
1 output, Z = X(s)
Multiplexers
C0
C1
C2
C3
4x1
MUX
s1 s0
Y
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A multiplexer is a
digital switch
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0 1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A 2 x 1 MUX
A
2x1
MUX
B
s0
Z
s0
Z
0
A
1
B
Behavior
if(s == 0)
Y = A;
else
Y = B;
A 2 x 1 MUX
A
2x1
MUX
B
Z
s0
Z
0
A
1
B
s0
Z = A & ~s0 | B & s0
A 4 x 1 MUX
C0
2x1
MUX
C1
A
A = ~s0 & C0 | s0 & C1
2x1
MUX
s0
B = ~s0 & C2 | s0 & C3
B
C2
2x1
MUX
Z = ~s1 & A | s1 & B
C3
Z = ~s1 & (~s0 & C0 | s0 & C1)
| s1 & (~s0 & C2 | s0 & C3)
s0
s1
Z
A 4 x 1 MUX
Z = ~s1 & (~s0 & C0 | s0 & C1)
| s1 & (~s0 & C2 | s0 & C3)
s1 s0
C0
C1
C2
4x1
MUX
C3
s1 s0
Z
0
0
1
1
0
1
0
1
Z = ~s1 & ~s0 &
Z | ~s1 & s0 &
| s1 & ~s0 &
C0 | s1 & s0 &
C1
C2
C3
C0
C1
C2
C3
A 4 x 1 MUX
s1 s0
C0
C1
C2
4x1
MUX
C3
s1 s0
Z
0
0
1
1
0
1
0
1
Z
C0
C1
C2
C3
case(s)
2'b00 :
2'b01 :
2'b10 :
2'b11 :
default:
endcase
Z
Z
Z
Z
Z
=
=
=
=
=
C0;
C1;
C2;
C3;
C0;
Problem
How would you make a
Quad 2-to-1 MUX?
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
s
Y
0
1
A
B
mux.v
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule
mux.v
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
always @(A,B,s)
if(s == 0)
Y = A;
else
Y = B;
endmodule
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
s
[Y3..Y0]
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
always @(A,B,s)
if(s == 0)
Y = A;
else
Y = B;
endmodule
Basic Combinational Circuits
•
•
•
•
•
•
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
– Gray Code Converter
– Binary-to-BCD Converter
7-Segment Display
D(3:0)
Truth table
D
0
1
2
3
4
5
6
7
a
1
0
1
1
0
1
1
1
b
1
1
1
1
1
0
0
1
c
1
1
0
1
1
1
1
1
d
1
0
1
1
0
1
1
0
e
1
0
1
0
0
0
1
0
f
1
0
0
0
1
1
1
0
g
0
0
1
1
1
1
1
0
D
8
9
A
b
C
d
E
F
a
1
1
1
0
1
0
1
1
b
1
1
1
0
0
1
0
0
c
1
1
1
1
0
1
0
0
d
1
1
0
1
1
1
1
0
seg7dec
e
1
0
1
1
1
1
1
1
f
1
1
1
1
1
0
1
1
g
1
1
1
1
0
1
1
1
AtoG(6:0)
7-Segment Display
Verilog
Behavior
D(3:0)
seg7dec
case(D)
0: AtoG =
1: AtoG =
2: AtoG =
3: AtoG =
4: AtoG =
5: AtoG =
6: AtoG =
7: AtoG =
8: AtoG =
9: AtoG =
'hA: AtoG =
'hb: AtoG =
'hC: AtoG =
'hd: AtoG =
AtoG(6:0) 'hE: AtoG =
'hF: AtoG =
default: AtoG
endcase
7'b1111110;
7'b0110000;
7'b1101101;
7'b1111001;
7'b0110011;
7'b1011011;
7'b1011111;
7'b1110000;
7'b1111111;
7'b1111011;
7'b1110111;
7'b0011111;
7'b1001110;
7'b0111101;
7'b1001111;
7'b1000111;
= 7'b1111110;
// 0
module hex7seg(D,AtoG);
input [3:0] D;
output [6:0] AtoG;
reg [6:0] AtoG;
always @(D)
case(D)
0:
1:
2:
3:
4:
5:
6:
7:
8:
9:
'hA:
'hb:
'hC:
'hd:
'hE:
'hF:
default:
endcase
endmodule
hex7seg.v
Verilog
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
7'b1111110;
7'b0110000;
7'b1101101;
7'b1111001;
7'b0110011;
7'b1011011;
7'b1011111;
7'b1110000;
7'b1111111;
7'b1111011;
7'b1110111;
7'b0011111;
7'b1001110;
7'b0111101;
7'b1001111;
7'b1000111;
7'b1111110;
a
f
b
g
e
c
d
// 0
Verilog
SW7seg.v
// Title
// Author
: Toggle switches to 7-Segment Display
: R. E. Haskell
module SW7seg(SW,LEDR,AtoG,AAtoGG);
input [7:0] SW;
SW(7..4)
output [7:0]LEDR;
output [6:0] AtoG;
output [6:0] AAtoGG;
wire [6:0] AtoG;
wire [6:0] AAtoGG;
wire [7:0] LEDR;
AAtoGG
d7L
hex7seg
AtoG
SW(3..0)
d7R
hex7seg
assign LEDR = SW;
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
endmodule
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
Wiring up the top-level design in Verilog
AAtoGG
SW(7..4)
D(3..0)
hex7seg
d7L
hex7seg
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
= AtoG
AtoG
SW(3..0)
d7R
[a,b,c,d,e,f,g]
hex7seg
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
#PACE: Start of PACE I/O Pin Assignments
NET "AAtoGG<0>" LOC = "p66" ;
NET "AAtoGG<1>" LOC = "p65" ;
NET "AAtoGG<2>" LOC = "p63" ;
NET "AAtoGG<3>" LOC = "p62" ;
NET "AAtoGG<4>" LOC = "p61" ;
NET "AAtoGG<5>" LOC = "p58" ;
NET "AAtoGG<6>" LOC = "p57" ;
NET "AtoG<0>" LOC = "p17" ;
NET "AtoG<1>" LOC = "p14" ;
NET "AtoG<2>" LOC = "p19" ;
NET "AtoG<3>" LOC = "p21" ;
NET "AtoG<4>" LOC = "p23" ;
NET "AtoG<5>" LOC = "p18" ;
NET "AtoG<6>" LOC = "p15" ;
NET "LEDR<0>" LOC = "p44" ;
NET "LEDR<1>" LOC = "p43" ;
NET "LEDR<2>" LOC = "p41" ;
NET "LEDR<3>" LOC = "p40" ;
NET "LEDR<4>" LOC = "p39" ;
NET "LEDR<5>" LOC = "p37" ;
NET "LEDR<7>" LOC = "p35" ;
NET "SW<0>" LOC = "p1" ;
NET "SW<1>" LOC = "p2" ;
NET "SW<2>" LOC = "p3" ;
NET "SW<3>" LOC = "p4" ;
NET "SW<4>" LOC = "p5" ;
NET "SW<5>" LOC = "p6" ;
NET "SW<6>" LOC = "p7" ;
NET "SW<7>" LOC = "p11" ;
SW7seg.ucf
hex7seg.v
Basic Combinational Circuits
•
•
•
•
•
•
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
– Gray Code Converter
– Binary-to-BCD Converter
Comparators
Recall that an XNOR gate can
be used as an equality detector
XNOR
X
Y
Z = X ~^ Y
xnor(Z,X,Y)
Z
if(X == Y)
Z = 1;
else
Z = 0;
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
1
Z = 1 if A=B=C
A
A=B
Z
A=B=C
B
C
B=C
A 1-Bit Comparator
x
Gout
Eout
Lout
y
1-bit
comparator
Gin
Lin
The variable Gout is 1 if x > y or if x = y and Gin = 1.
The variable Eout is 1 if x = y and Gin = 0 and Lin = 0.
The variable Lout is 1 if x < y or if x = y and Lin = 1.
The variable Gout is 1 if x > y or if x = y and Gin = 1.
The variable Eout is 1 if x = y and Gin = 0 and Lin = 0.
The variable Lout is 1 if x < y or if x = y and Lin = 1.
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
y
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Gin
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Lin
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gout
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
Eout
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Lout
0
1
0
1
1
1
1
1
0
0
0
0
0
1
0
1
Gout = x & ~y | x & Gin | ~y & Gin
Eout = ~x & ~y & ~Gin & ~Lin | x & y & ~Gin & ~Lin
Lout = ~x & y | ~x & Lin | y & Lin
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
y
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Gin
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Lin
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gout
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
Eout
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Lout
0
1
0
1
1
1
1
1
0
0
0
0
0
1
0
1
A 4-Bit Comparator
x3
gt
eq
lt
y3
G4
x2
x1
1-bit comp
L3
y1
G2
G3
1-bit comp
L4
y2
x0
G1
1-bit comp
L2
y0
G0
1-bit comp
L1
L0
Gin=0
Lin=0
Comparators
A[3:0]
A_EQ_B
comp
B[3:0]
A_GT_B
A_LT_B
module comp ( A ,B ,A_GT_B ,A_EQ_B, A_LT_B );
input [3:0] A ;
wire [3:0] A ;
input [3:0] B ;
wire [3:0] B ;
output A_LT_B ;
reg A_LT_B ;
output A_GT_B ;
reg A_GT_B ;
output A_EQ_B ;
reg A_EQ_B ;
always @(A or B)
begin
A_EQ_B = 0;
A_GT_B = 0;
A_LT_B = 0;
if(A == B)
A_EQ_B = 1;
if(A > B)
A_GT_B = 1;
if(A < B)
A_LT_B = 1;
end
endmodule
A[3:0]
comp
B[3:0]
A_EQ_B
A_GT_B
A_LT_B
Note: All outputs must be
assigned some value.
4-Bit Comparator
Basic Combinational Circuits
•
•
•
•
•
•
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
– Gray Code Converter
– Binary-to-BCD Converter
Full Adder
Truth table
Ci Ai Bi Si Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Ci
Ai
Bi
Combinational
Logic
Si
Ci+1
Behavior
Ci+1:Si = Ci + Ai + Bi
Full Adder
Ai
C i+1
Bi
Full Adder
Si
Block Diagram
Ci
4-Bit Adder
A3
B3
A2
Full Adder
Full Adder
4
S3
B1
S
1
0 1
0 0
1 0
B0
Full Adder
C0
C1
S2
C
0:A
0:B
C4:S
A0
Full Adder
C2
C3
C
A1
B2
1
1
1
1
S
1
1
0
1
0
0
1
1
0
0
0
module adder4(A,B,S,carry);
input [3:0] A;
A3 B 3
input [3:0] B;
output [3:0] S;
Full Adder
output carry;
reg [3:0] S;
reg carry;
reg [4:0] temp;
C
4
S3
adder.v
A2
A1
B2
Full Adder
B1
Full Adder
C2
C3
S2
A0
B0
Full Adder
C0
C1
S
1
S
0
Note: In the sensitivity list a
comma can be used in place of
or in Verilog 2001
always @(A, B)
begin
temp = {1'b0,A} + {1'b0,B};
S = temp[3:0];
carry = temp[4];
Concatenate a leading 0
end
endmodule
0
4-Bit Adder
Basic Combinational Circuits
•
•
•
•
•
•
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
– Gray Code Converter
– Binary-to-BCD Converter
3-to-8 Decoder
input [2:0] A ;
wire [2:0] A ;
Behavior
for(i = 0; i <= 7; i = i+1)
if(A == i)
Y[i] = 1;
else
Y[i] = 0;
output [0:7] Y ;
reg [0:7] Y ;
A2 A1 A0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
decode38.v
3-to-8 Decoder
module decode38 ( A, Y );
input [2:0] A ;
wire [2:0] A ;
output [0:7] Y ;
reg [0:7] Y ;
integer i;
always @(A)
for(i = 0; i <= 7; i = i+1)
if(A == i)
Y[i] = 1;
else
Y[i] = 0;
endmodule
3-to-8 Decoder
Basic Combinational Circuits
•
•
•
•
•
•
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
– Gray Code Converter
– Binary-to-BCD Converter
Gray Code
Definition: An ordering of 2n binary numbers such that
only one bit changes from one entry to the next.
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Gray coding {0...7}:
{000, 001, 011, 010, 110, 111, 101, 100}
Not unique
One method for generating a Gray code sequence:
Start with all bits zero and successively flip the
right-most bit that produces a new string.
Binary - Gray Code Conversions
Gray code: G[i], i = n – 1 : 0
Binary code: B[i], i = n – 1 : 0
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Gray coding {0...7}:
{000, 001, 011, 010, 110, 111, 101, 100}
Convert Binary to Gray:
Copy the most significant bit.
For each smaller i
G[i] = B[i+1] ^ B[i]
Convert Gray to Binary:
Copy the most significant bit.
For each smaller i
B[i] = B[i+1] ^ G[i]
bin2gray.v
module bin2gray ( B ,G );
input [3:0] B ;
wire [3:0] B ;
output [3:0] G ;
wire [3:0] G ;
assign G[3] = B[3];
assign G[2:0] = B[3:1] ^ B[2:0];
endmodule
Convert Binary to Gray:
Copy the most significant bit.
For each smaller i
G[i] = B[i+1] ^ B[i]
Binary to Gray Code Conversion
gray2bin.v
module gray2bin ( G ,B );
input [3:0] G ;
wire [3:0] G ;
output [3:0] B ;
reg [3:0] B ;
integer i;
Convert Gray to Binary:
Copy the most significant bit.
For each smaller i
B[i] = B[i+1] ^ G[i]
always @(G)
begin
B[3] = G[3];
for(i=2; i >= 0; i = i-1)
B[i] = B[i+1] ^ G[i];
end
endmodule
Gray Code to Binary Conversion
Basic Combinational Circuits
•
•
•
•
•
•
Multiplexers
7-Segment Decoder
Comparators
Adders
Decoders
Code Converters
– Gray Code Converter
– Binary-to-BCD Converter
Binary-to-BCD Conversion
• Shift and add 3 algorithm
• RTL solution
• Behavioral solution
Shift and Add-3 Algorithm
11.
22.
33.
44.
Shift the binary number left one bit.
If 8 shifts have taken place, the BCD number is in the
Hundreds, Tens, and Units column.
If the binary value in any of the BCD columns is 5 or greater,
add 3 to that value in that BCD column.
Go to 1.
Operation
HEX
Start
Hundreds
Tens
Units
Binary
F
1 1 1 1
F
1 1 1 1
Steps to convert an 8-bit binary number to BCD
Operation
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
Add 3
Shift 7
Add 3
Shift 8
BCD
P
z
Hundreds
Tens
Units
Binary
4
3
7
1
1
1 0
2
9 8
17 16
1
0
0
0
7
15
1
1 1
0 0
0 1
0 1
1 0
5
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
4
12
3
11
1
1 1
0 1
1 0
0 0
0 0
0 1
0 1
1 1
0 1
1 0
5
1
1
1
0
1
0
1
1
1
1
0
1
0
8
1
1
1
1
1
1
1
1
1
1
1
1
7
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
4
0
F
1 1 1 1
1 1 1
1 1
1
1
3
0
Truth table for Add-3 Module
A3 A2 A1 A0
C
S3 S2 S1 S0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S3
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
S2
0
0
0
0
1
0
0
0
0
1
X
X
X
X
X
X
S1
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
S0
0
1
0
1
0
0
1
0
1
0
X
X
X
X
X
X
K-Map for S3
A1 A0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S3
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
S2
0
0
0
0
1
0
0
0
0
1
X
X
X
X
X
X
S1
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
S0
0
1
0
1
0
0
1
0
1
0
X
X
X
X
X
X
A3 A2
00
01
11
10
1
1
1
00
01
11
X
X
X
X
10
1
1
X
X
S3 = A3
| A2 & A0
| A2 & A1
Binary-to-BCD
Converter
RTL Solution
Steps to convert a 6-bit binary number to BCD
Operation
1. Clear all bits of z to zero
2. Shift B left 3 bits
z[8:3] = B[5:0];
3. Do 3 times
if Units >4 then add 3 to Units
(note: Units = z[9:6])
Shift z left 1 bit
4. Tens = P[6:4] = z[12:10]
Units = P[3:0] = z[9:6]
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
BCD
P
z
Tens
Units
Binary
5 4 3 2 1 0
3
F
1 1 1 1 1 1
1
1 1
1 1 1 1 1
1 1 1 1
1 1 1
1 1 1
1 0 1 0
1 1 1
1
0 1 0 1
1 1
1
1 0 0 0
1 1
1 1
0 0 0 1
1
1 1 0
0 0 1 1
6
3
7
4
3
13
10 9
0
6 5
0
Operation
module binbcd6(B,P);
input [5:0] B;
output [6:0] P;
reg [6:0] P;
reg [12:0] z;
integer i;
binbcd6.v
always @(B)
begin
for(i = 0; i <= 12; i = i+1)
z[i] = 0;
z[8:3] = B;
for(i = 0; i <= 2; i = i+1)
begin
if(z[9:6] > 4)
z[9:6] = z[9:6] + 3;
z[12:1] = z[11:0];
end
P = z[12:6];
end
endmodule
Tens
Units
Binary
5 4 3 2 1 0
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
BCD
P
z
3
F
1 1 1 1 1 1
1
1 1 1 1 1
1 1
1 1 1 1
1 1 1
1 1 1
1 0 1 0
1 1 1
1
0 1 0 1
1 1
1
1 0 0 0
1 1
1 1
0 0 0 1
1
1 1 0
0 0 1 1
6
3
7
4
3
13
10 9
0
6 5
Hex 3F
6-bit binary input
0 B5 B4 B3 B2 B1 B0
1
1
1
1
0
1
1
1
1
1
C1
1
0
C2
1
0
0
0
C3
0
1
1
0
0
0
P7 P6 P5 P4 P3 P2 P1 P0
tens
units
6
3
0
binbcd6.v
Operation
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
BCD
P
z
Tens
Units
Hex 3F
6-bit binary input
0 B5 B4 B3 B2 B1 B0
Binary
1
5 4 3 2 1 0
3
F
1 1
1 0 1 0
1 1 1
1
0 1 0 1
1 1
1
1 0 0 0
1 1
1 1
0 0 0 1
1
1 1 0
0 0 1 1
4
3
13
10 9
1
0
1
1
1
1
1
C2
1
0
0
0
C3
0
1
1
0
0
0
P7 P6 P5 P4 P3 P2 P1 P0
3
7
0
1 1 1 1
1 1 1
6
1
1 1 1 1 1
1 1 1
1
C1
1 1 1 1 1 1
1
1
0
6 5
0
tens
units
6
3
BCD output
module binbcd8(B,P);
input [7:0] B;
output [9:0] P;
binbcd8.v
reg [9:0] P;
reg [17:0] z;
integer i;
always @(B)
begin
for(i = 0; i <= 17; i = i+1)
z[i] = 0;
z[10:3] = B;
Operation
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
Add 3
Shift 7
Add 3
Shift 8
BCD
P
z
for(i = 1; i <= 5; i = i+1)
begin
if(z[11:8] > 4)
z[11:8] = z[11:8] + 3;
if(z[15:12] > 4)
z[15:12] = z[15:12] + 3;
z[17:1] = z[16:0];
end
P = z[17:8];
end
endmodule
Hundreds
Tens
Units
Binary
4
3
7
1
1
1 0
2
9 8
17 16
1
0
0
0
7
15
1
0
0
0
1
1
1
0
1
1
0
5
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
4
12
3
11
1
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
5
1
1
1
0
1
0
1
1
1
1
0
1
0
8
1
1
1
1
1
1
1
1
1
1
1
1
7
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
4
0
F
1 1 1 1
1 1 1
1 1
1
1
3
0
binbcd8.v
Operation
B
HEX
Start
Shift 1
Shift 2
Shift 3
Add 3
Shift 4
Add 3
Shift 5
Shift 6
Add 3
Shift 7
Add 3
Shift 8
BCD
P
z
Hundreds
Tens
Units
Binary
4
3
7
1
1
1 0
2
9 8
17 16
1
0
0
0
7
15
1
0
0
0
1
1
1
0
1
1
0
5
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
0
4
12
3
11
1
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
5
1
1
1
0
1
0
1
1
1
1
0
1
0
8
1
1
1
1
1
1
1
1
1
1
1
1
7
F
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
1
1
1
1
1
1
1
1
4
0
F
1 1 1 1
1 1 1
1 1
1
1
3
0
module binbcd9(B,P);
input [8:0] B;
output [10:0] P;
9-bit Binary Input
binbcd9.v
0 B8 B7 B6 B5 B4 B3 B2 B1 B0
reg [10:0] P;
reg [19:0] z;
integer i;
always @(B)
begin
for(i = 0; i <= 19; i = i+1)
z[i] = 0;
z[11:3] = B;
for(i = 0; i <= 5; i = i+1)
begin
if(z[12:9] > 4)
z[12:9] = z[12:9] + 3;
if(z[16:13] > 4)
z[16:13] = z[16:13] + 3;
z[19:1] = z[18:0];
end
P = z[19:9];
end
endmodule
C1
C2
C3
0
C7
C4
C8
C5
C9
C6
P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Hundreds
Tens
Units
BCD Output
Figure 5. 9-bit Binary-to-BCD Converter
9-bit Binary Input
0 B8 B7 B6 B5 B4 B3 B2 B1 B0
binbcd9.v
C1
C2
C3
0
C7
C4
C8
C5
C9
C6
P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Hundreds
Tens
Units
BCD Output
Figure 5. 9-bit Binary-to-BCD Converter
16-bit
Binary-to-BCD
Converter
binbcd16.v
module binbcd16(B,P);
input [15:0] B;
output [18:0] P;
reg [18:0] P;
reg [31:0] z;
integer i;
always @(B)
begin
for(i = 0; i <= 31; i = i+1)
z[i] = 0;
z[18:3] = B;
for(i = 0; i <= 12; i = i+1)
begin
if(z[19:16] > 4)
z[19:16] = z[19:16]
if(z[23:20] > 4)
z[23:20] = z[23:20]
if(z[27:24] > 4)
z[27:24] = z[27:24]
if(z[31:28] > 4)
z[31:28] = z[31:28]
z[31:1] = z[30:0];
end
P = z[31:16];
end
endmodule
+ 3;
+ 3;
+ 3;
+ 3;
binbcd16.v