Transcript The GAL16V8 PLD - Oakland University

LEDs
7-Segment Displays
Discussion 7.2
Sections 10-2, 10-4, 13-8
Covalent bonds -- Insulator
http://electronics.howstuffworks.com/diode1.htm
Adding a very
small amount of
B or Ga to Si
makes a p-type
semi-conductor
with a missing
electron (a hole)
Semiconductors
Adding a very
small amount of
P or As to Si
makes an n-type
semi-conductor
with an extra
electron
Diodes
+
-
http://www.mtmi.vu.lt/pfk/funkc_dariniai/diod/index.html
Light Emmitting Diode
LED
hn
+
-
http://electronics.howstuffworks.com/led1.htm
Turning on an LED
No current
no light
+5V
R
LED
+5V
PLD output pin
1
light
Current
+1.7V
+5V
R
R=
voltage
current
+0.2V
LED
=
0
5 - 1.7
15 x 10
-3
PLD output pin
= 220 ohms
Turning on an LED
No Current
0
CPLD output pin
0V
no light
0V
R
LED
Current
light
1
CPLD output pin
+3.2 V
R=
voltage
current
=
R
3.2 - 1.9
4 x 10^-3
0V
+1.9 V
LED
= 325 ohms
R = 330 ohms
This is what
we use in Lab
7-Segment Display
+5V
a
Common
Anode
f
b
g
e
c
d
a
b
c
d
e
f
g
a
b
c
d
e
f
g
Common
Cathode
7-Segment Display
a
f
b
g
e
c
d
0
1
2
3
4
5
6
7
a
1
0
1
1
0
1
1
1
b
1
1
1
1
1
0
0
1
c
1
1
0
1
1
1
1
1
d
1
0
1
1
0
1
1
0
e
1
0
1
0
0
0
1
0
f
1
0
0
0
1
1
1
0
g
0
0
1
1
1
1
1
0
7-Segment Display
a
f
b
g
e
c
d
8
9
A
b
C
d
E
F
a
1
1
1
0
1
0
1
1
b
1
1
1
0
0
1
0
0
c
1
1
1
1
0
1
0
0
d
1
1
0
1
1
1
1
0
e
1
0
1
1
1
1
1
1
f
1
1
1
1
1
0
1
1
g
1
1
1
1
0
1
1
1
7-Segment Display
D(3:0)
Truth table
D
0
1
2
3
4
5
6
7
a
1
0
1
1
0
1
1
1
b
1
1
1
1
1
0
0
1
c
1
1
0
1
1
1
1
1
d
1
0
1
1
0
1
1
0
e
1
0
1
0
0
0
1
0
f
1
0
0
0
1
1
1
0
g
0
0
1
1
1
1
1
0
D
8
9
A
b
C
d
E
F
a
1
1
1
0
1
0
1
1
b
1
1
1
0
0
1
0
0
c
1
1
1
1
0
1
0
0
d
1
1
0
1
1
1
1
0
seg7dec
e
1
0
1
1
1
1
1
1
f
1
1
1
1
1
0
1
1
g
1
1
1
1
0
1
1
1
AtoG(6:0)
K-Map for Segment e
e = D3 & D2 | ~D2 & ~D0 | D3 & D1 | D1 & ~D0
D1 D0
00
D3 D2
00
D3 & D2
~D2 & ~D0
01
11
1
10
1
01
1
11
1
10
1
1
1
1
1
1
D3 & D1
D1 & ~D0
7-Segment Display
Verilog
Behavior
D(3:0)
seg7dec
case(D)
0: AtoG =
1: AtoG =
2: AtoG =
3: AtoG =
4: AtoG =
5: AtoG =
6: AtoG =
7: AtoG =
8: AtoG =
9: AtoG =
'hA: AtoG =
'hb: AtoG =
'hC: AtoG =
'hd: AtoG =
AtoG(6:0) 'hE: AtoG =
'hF: AtoG =
default: AtoG
endcase
7'b1111110;
7'b0110000;
7'b1101101;
7'b1111001;
7'b0110011;
7'b1011011;
7'b1011111;
7'b1110000;
7'b1111111;
7'b1111011;
7'b1110111;
7'b0011111;
7'b1001110;
7'b0111101;
7'b1001111;
7'b1000111;
= 7'b1111110;
// 0
module hex7seg(D,AtoG);
input [3:0] D;
output [6:0] AtoG;
reg [6:0] AtoG;
always @(D)
case(D)
0:
1:
2:
3:
4:
5:
6:
7:
8:
9:
'hA:
'hb:
'hC:
'hd:
'hE:
'hF:
default:
endcase
endmodule
hex7seg.v
Verilog
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
AtoG
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
7'b1111110;
7'b0110000;
7'b1101101;
7'b1111001;
7'b0110011;
7'b1011011;
7'b1011111;
7'b1110000;
7'b1111111;
7'b1111011;
7'b1110111;
7'b0011111;
7'b1001110;
7'b0111101;
7'b1001111;
7'b1000111;
7'b1111110;
a
f
b
g
e
c
d
// 0
Verilog
SW7seg.v
// Title
// Author
: Toggle switches to 7-Segment Display
: R. E. Haskell
module SW7seg(SW,LEDR,AtoG,AAtoGG);
input [7:0] SW;
SW(7..4)
output [7:0]LEDR;
output [6:0] AtoG;
output [6:0] AAtoGG;
wire [6:0] AtoG;
wire [6:0] AAtoGG;
wire [7:0] LEDR;
AAtoGG
d7L
hex7seg
AtoG
SW(3..0)
d7R
hex7seg
assign LEDR = SW;
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
endmodule
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
Wiring up the top-level design in Verilog
AAtoGG
SW(7..4)
D(3..0)
hex7seg
d7L
hex7seg
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
= AtoG
AtoG
SW(3..0)
d7R
[a,b,c,d,e,f,g]
hex7seg
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
Wiring up the top-level design in Verilog
AAtoGG
SW(7..4)
D(3..0)
hex7seg
d7L
hex7seg
[aa,bb,cc,dd,ee,ff,gg]
[a,b,c,d,e,f,g]
= AtoG
AtoG
SW(3..0)
d7R
[a,b,c,d,e,f,g]
hex7seg
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
#PACE: Start of PACE I/O Pin Assignments
NET "AAtoGG<0>" LOC = "p66" ;
NET "AAtoGG<1>" LOC = "p65" ;
NET "AAtoGG<2>" LOC = "p63" ;
NET "AAtoGG<3>" LOC = "p62" ;
NET "AAtoGG<4>" LOC = "p61" ;
NET "AAtoGG<5>" LOC = "p58" ;
NET "AAtoGG<6>" LOC = "p57" ;
NET "AtoG<0>" LOC = "p17" ;
NET "AtoG<1>" LOC = "p14" ;
NET "AtoG<2>" LOC = "p19" ;
NET "AtoG<3>" LOC = "p21" ;
NET "AtoG<4>" LOC = "p23" ;
NET "AtoG<5>" LOC = "p18" ;
NET "AtoG<6>" LOC = "p15" ;
NET "LEDR<0>" LOC = "p44" ;
NET "LEDR<1>" LOC = "p43" ;
NET "LEDR<2>" LOC = "p41" ;
NET "LEDR<3>" LOC = "p40" ;
NET "LEDR<4>" LOC = "p39" ;
NET "LEDR<5>" LOC = "p37" ;
NET "LEDR<7>" LOC = "p35" ;
NET "SW<0>" LOC = "p1" ;
NET "SW<1>" LOC = "p2" ;
NET "SW<2>" LOC = "p3" ;
NET "SW<3>" LOC = "p4" ;
NET "SW<4>" LOC = "p5" ;
NET "SW<5>" LOC = "p6" ;
NET "SW<6>" LOC = "p7" ;
NET "SW<7>" LOC = "p11" ;
SW7seg.ucf
hex7seg.v