Transcript Digilab2

7-Segment Display
DIO1 Board
Verilog
Digilab2 – DIO1 Boards
Four 7-segment
displays
A0
A1
A2
A3
DIO1 Board –
Common Anodes
Pins
Pins
A0 A1 A2 A3
AtoG(6:0)
Multiplex displays
1
0
0
0
0 0 0 0 1 1 0
Multiplex displays
0
1
0
0
0 0 0 1 1 1 1
Multiplex displays
0
0
1
0
1 0 0 1 1 0 0
Multiplex displays
0
0
0
1
0 1 1 1 0 0 0
x7seg
x7seg
x(15:12)
a
x(11:8)
b
x(7:4)
c
x(3:0)
d
digit(3:0)
y
seg7dec
AtoG(6:0)
sel
count(1:0)
clr
Acode
clr
cclk
Mux4
cclk
count
ctr2bit
A(3:0)
x7seg
x7seg.v
x(15:12)
a
x(11:8)
b
x(7:4)
c
x(3:0)
d
module x7seg(x,cclk,clr,AtoG,A);
input [15:0] x;
input cclk, clr;
output [6:0] AtoG;
output [3:0] A;
reg [6:0] AtoG;
reg [3:0] A;
integer k;
reg [3:0] digit;
reg [1:0] count;
digit(3:0)
y
seg7dec
AtoG(6:0)
sel
count(1:0)
clr
Acode
clr
cclk
Mux4
cclk
count
ctr2bit
A(3:0)
// ctr2bit
always @(posedge cclk or posedge clr)
if(clr)
count <= 0;
else
count <= count + 1;
x7seg
x(15:12)
a
x(11:8)
b
x(7:4)
c
x(3:0)
d
digit(3:0)
y
seg7dec
AtoG(6:0)
sel
count(1:0)
clr
Acode
clr
cclk
Mux4
cclk
count
ctr2bit
A(3:0)
// Mux4
always @(x,count)
case(count)
0: digit = x[15:12];
1: digit = x[11:8];
2: digit = x[7:4];
3: digit = x[3:0];
default: digit = x[3:0];
endcase
x7seg
x(15:12)
a
x(11:8)
b
x(7:4)
c
x(3:0)
d
digit(3:0)
y
seg7dec
AtoG(6:0)
sel
count(1:0)
clr
Acode
clr
cclk
Mux4
cclk
count
ctr2bit
A(3:0)
x(15:12)
a
x(11:8)
b
x(7:4)
c
x(3:0)
d
clr
clr
cclk
cclk
count
ctr2bit
// seg7dec
always @(digit)
case(digit)
0: AtoG =
1: AtoG =
2: AtoG =
x7seg
3: AtoG =
4: AtoG =
Mux4
digit(3:0)
5: AtoG =
seg7dec
AtoG(6:0)
y
6: AtoG =
sel
7: AtoG =
count(1:0)
8: AtoG =
Acode
A(3:0)
9: AtoG =
'hA: AtoG =
'hb: AtoG =
'hC: AtoG =
'hd: AtoG =
'hE: AtoG =
'hF: AtoG =
default: AtoG
endcase
7'b0000001;
7'b1001111;
7'b0010010;
7'b0000110;
7'b1001100;
7'b0100100;
7'b0100000;
7'b0001111;
7'b0000000;
7'b0000100;
7'b0001000;
7'b1100000;
7'b0110001;
7'b1000010;
7'b0110000;
7'b0111000;
= 7'b0000001;
// 0
// Acode
always @(count)
for(k = 0; k <= 3; k = k+1)
if(count == k)
A[k] = 1;
else
A[k] = 0;
x7seg
endmodule
Example:
count = 10
A[2] = 1
A[0] = A[1] = A[3] = 0
x(15:12)
a
x(11:8)
b
x(7:4)
c
x(3:0)
d
seg7dec
AtoG(6:0)
sel
Acode
clr
cclk
count
ctr2bit
A[3:0] = 0100
digit(3:0)
y
count(1:0)
clr
cclk
Mux4
A(3:0)
x7seg_test.v
module x7seg_test(mclk,bn,led,ldg,SW,AtoG,A);
input [1:8] SW;
input mclk, bn;
output ldg, led;
output [6:0] AtoG;
output [3:0] A;
wire [6:0] AtoG;
wire [3:0] A;
wire clr, cclk, bnbuf;
reg [23:0] clkdiv;
wire [7:0] fix;
IBUFG U00 (.I (bn), .O (bnbuf));
assign led = bnbuf;
assign clr = bnbuf;
assign ldg = 1;
// enable 74HC373 latch
// Divide the master clock (50Mhz)
always @(posedge mclk)
begin
clkdiv <= clkdiv + 1;
end
assign cclk = clkdiv[17];
assign fix = 8'b10100101;
// 190 Hz
x7seg
U1(.x({fix,SW}),.cclk(cclk),.clr(clr),.AtoG(AtoG),.A(A));
endmodule