Transcript Title

Hardware Description Languages
Digital Design and Computer Architecture
David Money Harris and Sarah L. Harris
Copyright © 2007 Elsevier
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Chapter 4 :: Topics
•
•
•
•
•
•
•
•
Introduction
Combinational Logic
Structural Modeling
Sequential Logic
More Combinational Logic
Finite State Machines
Parameterized Modules
Testbenches
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Introduction
• Hardware description language (HDL): allows
designer to specify logic function only. Then a
computer-aided design (CAD) tool produces or
synthesizes the optimized gates.
• Most commercial designs built using HDLs
• Two leading HDLs:
– Verilog
• developed in 1984 by Gateway Design Automation
• became an IEEE standard (1364) in 1995
– VHDL
• Developed in 1981 by the Department of Defense
• Became an IEEE standard (1076) in 1987
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HDL to Gates
• Simulation
– Input values are applied to the circuit
– Outputs checked for correctness
– Millions of dollars saved by debugging in simulation instead of
hardware
• Synthesis
– Transforms HDL code into a netlist describing the hardware (i.e.,
a list of gates and the wires connecting them)
IMPORTANT:
When describing circuits using an HDL, it’s critical to
think of the hardware the code should produce.
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Verilog Example
Verilog:
module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b &
endmodule
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c;
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Verilog Simulation
Verilog:
module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b &
endmodule
Copyright © 2007 Elsevier
c;
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Verilog Synthesis
Verilog:
module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b &
endmodule
c;
Synthesis:
b
c
y
un5_y
y
a
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un8_y
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Verilog Syntax
• Case sensitive
– Example: reset and Reset are not the same signal.
• No names that start with numbers
– Example: 2mux is an invalid name.
• Whitespace ignored
• Comments:
– // single line comment
– /* multiline
comment */
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Boolean Equations in Verilog
• Use logical operators in assignment statements
module circuit ( output f,
input x, y, z );
assign f = (x | (y & ~z)) & ~(y & z);
endmodule
• What is the synthesized logic?
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Structural Modeling - Hierarchy
module and3(input a, b, c,
output y);
assign y = a & b & c;
endmodule
También se puede escribir: and3 andgate(.y(n1), .a(a), .b(b),.c(c))
module inv(input a,
output y);
assign y = ~a;
endmodule
module nand3(input a, b, c
output y);
wire n1;
// internal signal
and3 andgate(a, b, c, n1); // instance of and3
inv inverter(n1, y);
// instance of inverter
endmodule
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Bitwise Operators
module gates(input [3:0] a, b,
output [3:0] y1, y2, y3, y4, y5);
/* Five different two-input logic
gates acting on 4 bit busses */
assign y1 = a & b;
// AND
assign y2 = a | b;
// OR
assign y3 = a ^ b;
// XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
//
/*…*/
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single line comment
multiline comment
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Reduction Operators
module and8(input [7:0] a,
output
y);
assign y = &a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] &
//
a[3] & a[2] & a[1] & a[0];
endmodule
Copyright © 2007 Elsevier
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Boolean Equation Example
• Air conditioner control logic
module aircon ( output heater_on, cooler_on, fan_on,
input temp_low, temp_high, auto_temp,
input manual_heat, manual_cool, manual_fan );
assign heater_on = (temp_low & auto_temp) | manual_heat;
assign cooler_on = (temp_high & auto_temp) | manual_cool;
assign fan_on
= heater_on | cooler_on | manual_fan;
endmodule
• What is the synthesized Logic?
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Copyright © 2007 Elsevier
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Conditional Assignment
module mux2(input [3:0] d0, d1,
input
s,
output [3:0] y);
assign y = s ? d1 : d0;
endmodule
? :
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is also called a ternary operator because it
operates on 3 inputs: s, d1, and d0.
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Internal Variables
module fulladder(input a, b, cin, output s, cout);
wire p, g;
// internal nodes
assign p = a ^ b;
assign g = a & b;
assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule
s
g
s
cin
cout
a
b
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p
un1_cout
cout
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Precedence
Defines the order of operations
Highest
~
NOT
*, /, %
mult, div, mod
+, -
add,sub
<<, >>
shift
<<<, >>>
arithmetic shift
<, <=, >, >= comparison
Lowest
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==, !=
equal, not equal
&, ~&
AND, NAND
^, ~^
XOR, XNOR
|, ~|
OR, XOR
?:
ternary operator
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Verilog Logical Operators
a & b
a b
a | b
ab
~(a & b)
a b
~(a | b)
ab
a ^ b
ab
a ~^ b
ab
~a
a
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• Precedence
– not has highest
– then &, then ^ and ~^, then |
– use parentheses to make order
of evaluation clear
• Verilog bit values
– 1'b0 and 1'b1
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Numbers
Format: N'Bvalue
N = number of bits, B = base
N'B is optional but recommended (default is decimal)
Number
# Bits
Base
Decimal
Equivalent
Stored
3’b101
3
binary
5
101
‘b11
unsized
binary
3
00…0011
8’b11
8
binary
3
00000011
8’b1010_1011
8
binary
171
10101011
3’d6
3
decimal
6
110
6’o42
6
octal
34
100010
8’hAB
8
hexadecimal
171
10101011
42
Unsized
decimal
42
00…0101010
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Scaling in Verilog
• Shift-left (<<) and shift-right (>>) operations
– result is same size as operand
s = 000100112 = 1910
s = 000100112 = 1910
assign y = s << 2;
assign y = s >> 2;
y = 010011002 = 7610
y = 000001002 = 410
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4-<21>
Bit Manipulations: Example 1
assign y = {a[2:1], {3{b[0]}}, a[0], 6’b100_010};
// if y is a 12-bit signal, the above statement produces:
y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0
// underscores (_) are used for formatting only to make
it easier to read. Verilog ignores them.
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Bit Manipulations: Example 2
Verilog:
module mux2_8(input [7:0] d0, d1,
input
s,
output [7:0] y);
mux2 lsbmux(.d0(d0[3:0]), .d1(d1[3:0]), .s(s), .y(y[3:0]));
mux2 msbmux(.d0(d0[7:4]), .d1(d1[7:4]), .s(s), .y(y[7:4]));
endmodule
Synthesis:
mux2
s
s
d0[7:0]
[7:0]
[3:0]
d0[3:0]
d1[7:0]
[7:0]
[3:0]
d1[3:0]
y[3:0]
[3:0]
[7:0]
y[7:0]
lsbmux
mux2
s
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[7:4]
d0[3:0]
[7:4]
d1[3:0]
y[3:0]
msbmux
[7:4]
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Z: Floating Output
Verilog:
module tristate(input [3:0] a,
input
en,
output [3:0] y);
assign y = en ? a : 4'bz;
endmodule
Synthesis:
en
a[3:0]
[3:0]
[3:0]
[3:0]
[3:0]
y[3:0]
y_1[3:0]
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4-<24>
Other Behavioral Statements
• Statements that must be inside always statements:
– if / else
– case, casez
• Reminder: Variables assigned in an always
statement must be declared as reg (even if they’re
not actually registered!)
Copyright © 2007 Elsevier
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Combinational Logic using always
// combinational logic using an always statement
module gates(input
[3:0] a, b,
output reg [3:0] y1, y2, y3, y4, y5);
always @(*)
// need begin/end because there is
begin
// more than one statement in always
y1 = a & b;
// AND
y2 = a | b;
// OR
y3 = a ^ b;
// XOR
y4 = ~(a & b); // NAND
y5 = ~(a | b); // NOR
end
endmodule
This hardware could be described with assign statements using fewer lines of
code, so it’s better to use assign statements in this case.
Copyright © 2007 Elsevier
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Combinational Components
• We can build complex combination components
from gates
– Decoders, encoders
– Multiplexers
– …
• Use them as subcomponents of larger systems
– Abstraction and reuse
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Decoders
• A decoder derives control signals from a
binary coded signal
– One per code word
– Control signal is 1 when input has the
corresponding code word; 0 otherwise
y0
y1
y2
y3
y4
y15
• For an n-bit code input
…
…
a0
a1
a2
a3
– Decoder has 2n outputs
• Example: (a3, a2, a1, a1)
– Output for (1, 0, 1, 1):
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y11  a3  a2  a1  a0
4-<30>
Decoder Example
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Color
Codeword (c2, c1, c0)
black
0, 0, 1
cyan
0, 1, 0
magenta
0, 1, 1
yellow
1, 0, 0
red
1, 0, 1
blue
1, 1, 0
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Decoder Example
module ink_jet_decoder
( output black, cyan, magenta, yellow,
light_cyan, light_magenta,
input color2, color1, color0 );
assign
assign
assign
assign
assign
assign
black
cyan
magenta
yellow
light_cyan
light_magenta
= ~color2 & ~color1 & color0;
= ~color2 & color1 & ~color0;
= ~color2 & color1 & color0;
= color2 & ~color1 & ~color0;
= color2 & ~color1 & color0;
= color2 & color1 & ~color0;
endmodule
Copyright © 2007 Elsevier
4-<32>
Encoders
• An encoder encodes which of
several inputs is 1
…
…
a0
a1
a2
a3
a4
a15
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y0
y1
y2
y3
valid
– Assuming (for now) at most one
input is 1 at a time
• What if no input is 1?
– Separate output to indicate this
condition
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Encoder Example
• Burglar alarm: encode
which zone is active
Copyright © 2007 Elsevier
Zone
Zone 1
Codeword
0, 0, 0
Zone 2
Zone 3
Zone 4
0, 0, 1
0, 1, 0
0, 1, 1
Zone 5
Zone 6
Zone 7
Zone 8
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
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Encoder Example
module alarm_eqn ( output [2:0] intruder_zone,
output
valid,
input [1:8] zone );
assign intruder_zone[2] = zone[5]
zone[7]
assign intruder_zone[1] = zone[3]
zone[7]
assign intruder_zone[0] = zone[2]
zone[6]
|
|
|
|
|
|
zone[6] |
zone[8];
zone[4] |
zone[8];
zone[4] |
zone[8];
assign valid = zone[1] | zone[2] | zone[3] | zone[4] |
zone[5] | zone[6] | zone[7] | zone[8];
endmodule
Copyright © 2007 Elsevier
4-<35>
Priority Encoders
• If more than one input can be 1
– Encode input that is 1 with highest priority
zone
intruder_zone
valid
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(2)
(1)
(0)
1
–
–
–
–
–
–
–
0
0
0
1
0
1
–
–
–
–
–
–
0
0
1
1
0
0
1
–
–
–
–
–
0
1
0
1
0
0
0
1
–
–
–
–
0
1
1
1
0
0
0
0
1
–
–
–
1
0
0
1
0
0
0
0
0
1
–
–
1
0
1
1
0
0
0
0
0
0
1
–
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
–
–
–
0
Copyright © 2007 Elsevier
4-<36>
Priority Encoder Example
module alarm_priority_1 ( output [2:0] intruder_zone,
output
valid,
input [1:8] zone );
assign intruder_zone = zone[1]
zone[2]
zone[3]
zone[4]
zone[5]
zone[6]
zone[7]
zone[8]
3'b000;
?
?
?
?
?
?
?
?
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
:
:
:
:
:
:
:
:
assign valid = zone[1] | zone[2] | zone[3] | zone[4] |
zone[5] | zone[6] | zone[7] | zone[8];
endmodule
Copyright © 2007 Elsevier
4-<37>
BCD Code
• Binary coded decimal
– 4-bit code for decimal digits
0: 0000
1: 0001
2: 0010
3: 0011
4: 0100
5: 0101
6: 0110
7: 0111
8: 1000
9: 1001
Copyright © 2007 Elsevier
4-<38>
Combinational Logic using case
• In order for a case statement to imply combinational
logic, all possible input combinations must be described by
the HDL.
• Remember to use a default statement when necessary.
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4-<39>
Seven-Segment Decoder
• Decodes BCD to drive a 7-segment LED or LCD
display digit
– Segments: (g, f, e, d, c, b, a)
a
f
e
g
d
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b
0111111
0000110
1011011
1001111
1100110
1101101
1111101
0000111
1111111
1101111
c
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Seven-Segment Decoder
module seven_seg_decoder ( output [7:1] seg,
input [3:0] bcd, input blank );
reg [7:1] seg_tmp;
always @*
case (bcd)
4'b0000:
4'b0001:
4'b0010:
4'b0011:
4'b0100:
4'b0101:
4'b0110:
4'b0111:
4'b1000:
4'b1001:
default:
endcase
seg_tmp
seg_tmp
seg_tmp
seg_tmp
seg_tmp
seg_tmp
seg_tmp
seg_tmp
seg_tmp
seg_tmp
seg_tmp
=
=
=
=
=
=
=
=
=
=
=
7'b0111111;
7'b0000110;
7'b1011011;
7'b1001111;
7'b1100110;
7'b1101101;
7'b1111101;
7'b0000111;
7'b1111111;
7'b1101111;
7'b1000000;
//
//
//
//
//
//
//
//
//
//
//
0
1
2
3
4
5
6
7
8
9
"-" for invalid code
assign seg = blank ? 7'b0000000 : seg_tmp;
endmodule
Copyright © 2007 Elsevier
4-<41>
Blocking vs. Nonblocking Assignments
• <= is a “nonblocking assignment”
– Occurs simultaneously with others
• = is a “blocking assignment”
– Occurs in the order it appears in the file
// Good synchronizer using
// nonblocking assignments
module syncgood(input
clk,
input
d,
output reg q);
reg n1;
always @(posedge clk)
begin
n1 <= d; // nonblocking
q <= n1; // nonblocking
end
endmodule
Copyright © 2007 Elsevier
// Bad synchronizer using
// blocking assignments
module syncbad(input
clk,
input
d,
output reg q);
reg n1;
always @(posedge clk)
begin
n1 = d; // blocking
q = n1; // blocking
end
endmodule
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Adders in Verilog
• Use arithmetic “+” operator
wire [7:0] a, b, s;
...
assign s = a + b;
wire [8:0] tmp_result;
wire
c;
...
assign tmp_result = {1'b0, a} + {1'b0, b};
assign c
= tmp_result[8];
assign s
= tmp_result[7:0];
assign {c, s} = {1'b0, a} + {1'b0, b};
assign {c, s} = a + b;
Copyright © 2007 Elsevier
4-<44>
Increment/Decrement in Verilog
• Just add or subtract 1
wire [15:0] x, s;
...
assign s = x + 1;
// increment x
assign s = x - 1;
// decrement x
• Note: 1 (integer), not 1'b1 (bit)
– Automatically resized
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4-<45>
Equality Comparison
• XNOR gate: equality of two bits
– Apply bitwise to two unsigned numbers
• In Verilog, x == y gives a bit
result
x0
y0
x1
y1
– 1'b0 for false, 1'b1 for true
…
eq
…
xn–1
yn–1
Copyright © 2007 Elsevier
assign eq = x == y;
4-<46>
Inequality Comparison
• Magnitude comparator for x > y
xn–1 > yn–1
xn–1
yn–1
gt
xn–1 = yn–1
xn–2 > yn–2
xn–2
yn–2
xn–2…0 > yn–2…0
xn–2 = yn–2
x1 > y1
…
…
…
x1
y1
x1…0 > y1…0
x1 = y1
x0
y0
Copyright © 2007 Elsevier
x0 > y0
4-<47>
Comparison Example in Verilog
• Thermostat with target termperature
– Heater or cooler on when actual temperature is more
than 5° from target
module thermostat ( output
heater_on, cooler_on,
input [7:0] target, actual );
assign heater_on = actual < target - 5;
assign cooler_on = actual > target + 5;
endmodule
• How is it synthesized?
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4-<48>
Sequential Logic
• Verilog uses certain idioms to describe latches, flip-flops and
FSMs
• Other coding styles may simulate correctly but produce
incorrect hardware
Copyright © 2007 Elsevier
4-<49>
Rules for Signal Assignment
• Use always @(posedge clk) and nonblocking
assignments (<=) to model synchronous sequential logic
always @ (posedge clk)
q <= d; // nonblocking
• Use continuous assignments (assign …)to model simple
combinational logic.
assign y = a & b;
• Use always @ (*) and blocking assignments (=) to
model more complicated combinational logic where the
always statement is helpful.
• Do not make assignments to the same signal in more than one
always statement or continuous assignment statement.
Copyright © 2007 Elsevier
4-<50>
D Flip-Flop
module flop(input
clk,
input
[3:0] d,
output reg [3:0] q);
always @ (posedge clk)
q <= d;
// pronounced “q gets d”
endmodule
Any signal assigned in an always statement must be declared reg. In
this case q is declared as reg
Beware: A variable declared reg is not necessarily a registered output.
We will show examples of this later.
Copyright © 2007 Elsevier
4-<51>
Resettable D Flip-Flop
module flopr(input
clk,
input
reset,
input
[3:0] d,
output reg [3:0] q);
// synchronous reset
always @ (posedge clk)
if (reset) q <= 4'b0;
else
q <= d;
endmodule
clk
d[3:0]
reset
[3:0]
[3:0]
D[3:0]
R
Q[3:0]
[3:0]
[3:0]
q[3:0]
q[3:0]
Copyright © 2007 Elsevier
4-<52>
Resettable D Flip-Flop
module flopr(input
clk,
input
reset,
input
[3:0] d,
output reg [3:0] q);
// asynchronous reset
always @ (posedge clk, posedge reset)
if (reset) q <= 4'b0;
else
q <= d;
endmodule
clk
d[3:0]
[3:0]
[3:0]
D[3:0]
Q[3:0]
[3:0]
[3:0]
q[3:0]
R
reset
Copyright © 2007 Elsevier
q[3:0]
4-<53>
D Flip-Flop with Enable
module flopren(input
clk,
input
reset,
input
en,
input
[3:0] d,
output reg [3:0] q);
// asynchronous reset and enable
always @ (posedge clk, posedge reset)
if
(reset) q <= 4'b0;
else if (en)
q <= d;
endmodule
Copyright © 2007 Elsevier
4-<54>
Latch
module latch(input
clk,
input
[3:0] d,
output reg [3:0] q);
always @ (clk, d)
if (clk) q <= d;
endmodule
d[3:0]
clk
[3:0]
[3:0]
lat
D[3:0]
C
Q[3:0]
[3:0]
[3:0]
q[3:0]
q[3:0]
Warning: We won’t use latches in this course, but you might write code that
inadvertently implies a latch. So if your synthesized hardware has latches in it,
this indicates an error.
Copyright © 2007 Elsevier
4-<55>