Transcript INTRODUCTION TO VERILOG HDL
INTRODUCTION TO VERILOG HDL
Presented by m.vinoth
What is verilog?
• Verilog is a HDL- hardware description language to design the digital system.
• VHDL is other hardware description language.
• Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages • Verilog was introduced in 1985 by Gateway Design System Corporation
verilog
• IEEE 1364-2001 is the latest Verilog HDL standard • Verilog is case sensitive (Keywords are in lowercase) • The Verilog is both a behavioral and a structure language
Difference between VERILOG and VHDL
• Verilog is similar to c- language.
• VHDL is similar to Ada- (ada is a structured , statically typed , imperative , wide-spectrum , and object-oriented high level computer programming language , extended from Pascal ) • Many feel that Verilog is easier to learn and use than VHDL.
Elements of verilog-logic values
0: zero, logic low, false, ground 1: one, logic high, power • X: unknown • Z: high impedance, unconnected, tri-state
Elements of verilog- data type
• • Nets – Nets are physical connections between devices – Many types of nets, but all we care about is wire.
Declaring a net wire [
Default is one bit wide
• Registers – Implicit storage-holds its value until a new value is assigned to it.
• – Register type is denoted by reg.
Declaring a register reg [
Parameters
are not variables, they are constants.
Verilog Primitives
• Basic logic gates only – and – or – not – buf – xor – nand – nor – xnor – bufif1, bufif0 – notif1, notif0
Numbers in Verilog
Logical Operators
• && • || • ! logical AND logical OR logical NOT • Operands evaluated to ONE bit value:
0
,
1
or
x
• Result is ONE bit value:
0
,
1
or
x
A = 1; B = 0; C = x; A && B 1 && 0 0 A || !B C || B 1 || 1 x || 0 x 1 but C&&B=0
Bitwise Operators (i)
• & • | • ~ • ^ • ~^ or ^~ bitwise AND bitwise OR bitwise NOT bitwise XOR bitwise XNOR • Operation on bit by bit basis
Bitwise Operators (ii)
c = ~a; c = a & b; • a = 4’b1010; b = 4’b1100; c = a ^ b; • a = 4’b1010; b = 2’b11;
shift, Conditional Operator
• >> • << shift right shift left • a = 4’b1010; d = a >> 2;// d = 0010,c = a << 1;// c = 0100 • cond_expr ? true_expr : false_expr A 1 Y Y = (sel)? A : B; B 0 sel
keywords
• Note : All keywords are defined in • Examples • parameter • begin, end • fork, join : • module, endmodule • input, output, inout • reg, integer, real, time • not, and, nand, or, nor, xor • specify, endspecify lower case
keywords
• module – fundamental building block for Verilog designs • Used to construct design hierarchy • Cannot be nested • endmodule – ends a module – not a statement • => no “ ; module ” • Module Declaration
module_name …
); • Example: module (
module_port
,
module_port
, full_adder (A, B, c_in, c_out, S);
Verilog keywords
• Input Declaration • Scalar • input
list of input identifiers
; • Example: input A, B, c_in; • Vector • input [
range
] • Example:
list of input identifiers
; input[15:0] A, B, data; • Output Declaration • Scalar Example: output c_out, OV, MINUS; • Vector Example: output [7:0] ACC, REG_IN, data_out;
Types verilog coding
•
Behavioral
Procedural code, similar to C programming Little structural detail (except module interconnect) •
Dataflow
Specifies transfer of data between registers Some structural information is available (RTL) Sometimes similar to behavior •
Structural (gate,switch)
Interconnection of simple components Purely structural
Hierarchical Design
Top Level Module Sub-Module 1 Sub-Module 2 Basic Module 1 Basic Module 2 Basic Module 3 E.g.
Full Adder Half Adder Half Adder
Module
in1 in2 my_module inN f out1 out2 module my_module(out1, .., inN); output out1, .., outM; input in1, .., inN; outM .. // declarations .. // description of f (maybe .. // sequential) endmodule Everything you write in Verilog must be inside a module exception: compiler directives
VHDL coding for AND gate
• • • • • • • • • • • • • • • • --The IEEE standard 1164 package, declares std_logic, etc.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; ---------------------------------- Entity Declarations ------------------------ entity andgate is Port( A : in std_logic; B : in std_logic; Y : out std_logic ); end andgate; architecture Behavioral of andgate is begin Y<= A and B ; end Behavioral;
VERILOG coding for all gate
• module gates(a, b, y1, y2, y3, y4, y5, y6, y7); • input [3:0] a, b; • output [3:0] y1, y2, y3, y4, y5, y6, y7; • /* Seven different logic gates acting on four bit busses */ • assign y1= ~a; // NOT gate • assign y2= a & b; // AND gate • assign y3= a | b; // OR gate • assign y4= ~(a & b); // NAND gate • assign y5= ~(a | b); // NOR gate • assign y6= a ^ b; // XOR gate • assign y7= ~(a ^ b); // XNOR gate • endmodule
Example: Half Adder
A B S C A B Half Adder S C module half_adder(S, C, A, B); output S, C; input A, B; wire S, C, A, B; assign S = A ^ B; assign C = A & B; endmodule
in1 A in2 B
Example: Full Adder
Half Adder 1 ha1 S I1 C I2 A B Half Adder ha2 S C I3 cin Module name module full_adder(sum, cout, in1, in2, cin); output sum, cout; input in1, in2, cin; wire sum, cout, in1, in2, cin; wire I1, I2, I3; Instance name half_adder ha1(I1, I2, in1, in2); half_adder ha2(sum, I3, I1, cin); assign cout = I2 || I3; endmodule sum cout
• 4-bit adder
Example
module add4 (s,c3,ci,a,b) input [3:0] a,b ; // port declarations input ci ; output [3:0] s : // vector output c3 ; wire [2:0] co ; add a0 (co[0], s[0], a[0], b[0], ci) ; add a1 (co[1], s[1], a[1], b[1], co[0]) ; add a2 (co[2], s[2], a[2], b[2], co[1]) ; add a3 (c3, s[3], a[3], b[3], co[2]) ; endmodule c3 Simpler than VHDL Only Syntactical Difference a3 a2 a1 a0 ci
Assignments
• Continuous assignments assign values to nets (vector and scalar) – They are triggered whenever simulation causes the value of the right-hand side to change – Keyword “assign” e.g.
assign
out = in1 & in2; • Procedural assignments drive values onto registers (vector and scalar) – They Occur within procedures such as
always
and
initial
– They are triggered when the flow of execution reaches them (like in C) – Blocking and Non-Blocking procedural assignments
Assignments (cont.)
• Procedural Assignments –
Blocking assignment
statement (
=
operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement –
Nonblocking
assignment statement (
<=
operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit
Delay based Timing Control
•
Delay Control ( # )
– Expression specifies the time duration between initially encountering the statement and when the statement actually executes.
– Delay in Procedural Assignments • Inter-Statement Delay • Intra-Statement Delay – For example: • Inter-Statement Delay #10 A = A + 1; • Intra-Statement Delay A = #10 A + 1;
A B
Example: Half Adder, 2nd Implementation
S C Assuming: • XOR: 2 t.u. delay • AND: 1 t.u. delay module half_adder(S, C, A, B); output S, C; input A, B; wire S, C, A, B; xor #2 (S, A, B); and #1 (C, A, B); endmodule
Combinational Circuit Design
• Outputs are functions of inputs inputs comb.
circuits • Examples – MUX – decoder – priority encoder – adder Outputs
Procedural Statements: if
if (expr1) true_stmt1; else if (expr2) true_stmt2; ..
else def_stmt; E.g. 4-to-1 mux: module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel; always @(in or sel) if (sel == 0) out = in[0]; else if (sel == 1) out = in[1]; else if (sel == 2) out = in[2]; else out = in[3]; endmodule
Procedural Statements: case
case (expr) item_1, .., item_n: stmt1; item_n+1, .., item_m: stmt2; ..
default: def_stmt; endcase E.g. 4-to-1 mux: module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel; always @(in or sel) case (sel) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcase endmodule
Decoder
• 3-to 8 decoder with an enable control module decoder(o,enb_,sel) ; output [7:0] o ; input enb_ ; input [2:0] sel ; reg [7:0] o ; always @ (enb_ or sel) if(enb_) o = 8'b1111_1111 ; else case(sel) 3'b000 : o = 8'b1111_1110 ; 3'b001 : o = 8'b1111_1101 ; 3'b010 : o = 8'b1111_1011 ; 3'b011 : o = 8'b1111_0111 ; 3'b100 : o = 8'b1110_1111 ; 3'b101 : o = 8'b1101_1111 ; 3'b110 : o = 8'b1011_1111 ; 3'b111 : o = 8'b0111_1111 ; default : o = 8'bx ; endcase endmodule
Inputs
Sequential Circuit Design
Outputs Combinational circuit Memory elements – a feedback path – the state of the sequential circuits – the state transition synchronous circuits asynchronous circuits Examples D latch D flip-flop register
d-Latch,flip-flop
• • • • • • • • • • module latch (G, D, Q); input G, D; output Q; reg Q; always @(G or D) begin if (G) Q <= D; end endmodule module dff(Q, D, Clk); output Q; input D, Clk; reg Q; wire D, Clk; always @(posedge Clk) Q = D; endmodule
Jk flip-flop
module jkff(J, K, clk, Q); input J, K, clk; output Q; reg Q; reg Qm; always @(posedge clk) if(J == 1 && K == 0)
Qm <= 1;
else if(J == 0 && K == 1)
Qm <= 0;
else if(J == 1 && K == 1)
Qm <= ~Qm; assign Q <= Qm;
endmodule
A counter which runs through counts 0, 1, 2, 4, 9, 10, 5, 6, 8, 7, 0, … • • • • • • • • • • • • • • • • • • • • • • • • • • Sequence counter
module CntSeq(clk, reset, state); parameter n = 4; input clk, reset; output [n-1:0]state; reg1:0]state;
[n-
integer k;
//
always @(posedge clk)
if(reset) state = 0; else
begin
case (state) 4'b0000:state = 4'b0001; //0 -> 1 4'b0001:state = 4'b0010; //1 -> 2 4'b0010:state = 4'b0100; //2 -> 4 4'b0100:state = 4'b1001; //4 -> 9 4'b1001:state = 4'b1010; //9 -> 10 4'b1010:state = 4'b0101; //10-> 5 4'b0101:state = 4'b0110; //5 -> 6 4'b0110:state = 4'b1000; //6 -> 8 4'b1000:state = 4'b0111; //8 -> 7 default:state = 4'b0000; endcase
end endmodule