Transcript Slide 1

RT Level Design


RT level design:
 Taking a high level description of a design
 Partitioning
 Coming up with an architecture
 Designing the bussing structure
 Describing and implementing various components of the
architecture
Steps in RT level design:
 Control/Data Partitioning
 Data Part Design
 Control Part Design
Verilog Digital System Design
Z. Navabi, 2006
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RT Level Design
RT Level
Design
Control/data
Partitioning
Data Part
Control Part
Verilog Digital System Design
Z. Navabi, 2006
2
Control/Data Partitioning
RT Level
Design
Control/data
Control/data
Partitioning
Partitioning
Data Part
Control Part
Verilog Digital System Design
Z. Navabi, 2006
3
Control/Data Partitioning
RT Level Design
Control
DataPath
Reg
Flags & status
Data Inputs
Opcode
Control
Outputs
Data flow
Control signals
Control
Data Outputs
Inputs
Verilog Digital System Design
Z. Navabi, 2006
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Data Part
RT Level
Design
Control/data
Partitioning
Data Part
Part
Data
Control Part
Verilog Digital System Design
Z. Navabi, 2006
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Data Part
DataPath
Reg
Flags & status
Data Inputs
Opcode
Data flow
Control signals
Data Outputs
Verilog Digital System Design
Z. Navabi, 2006
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Data Part
Output Signals: Going
to the control part,
provide flags and
status of the data
module DataPath
(DataInput, DataOutput, Flags, Opcodes,
ControlSignals);
input
[15:0] DataInputs;
Control Signals:
output [15:0] DataOutputs;
Inputs to data part,
output Flags, ...;
sent to the data
output Opcodes, ...;
components and
input
ControlSignals, ...;
busses
// instantiation of data components
// ...
// interconnection of data components
// bussing specification
endmodule
 DataPath Module
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Data Part
module DataComponent
(DataIn, DataOut, ControlSignals);
Data Component:
Shows how the
component uses its
input control
signals to perform
various operations
on its data inputs
input [7:0] DataIn;
output [7:0] DataOut;
input ControlSignals;
// Depending on ControlSignals
// Operate on DataIn and
// Produce DataOut
endmodule
 Partial Verilog Code of a Data Component
Verilog Digital System Design
Z. Navabi, 2006
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Control Part
RT Level
Design
Control/data
Partitioning
Data Part
Control Part
Control
Part
Verilog Digital System Design
Z. Navabi, 2006
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Control Part
Control
Flags & status
Control
Outputs
Opcode
Data flow
Control signals
Control
Inputs
Makes decisions as
to when and what
control signals to
issue depending on
its state.
Consists of one or
more state machines
to keep the state of
the circuit.
Verilog Digital System Design
Z. Navabi, 2006
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Control Part
module ControlUnit
(Flags, Opcodes, ExternalControls, ControlSignals);
input Flags, ...;
Takes control
input Opcodes, ...;
inputs from the
input ExternalControls, ...;
Data Part
output ControlSignals;
// Based on inputs decide :
// What control signals to issue,
// and what next state to take
endmodule
 Outline of a Controller
Verilog Digital System Design
Z. Navabi, 2006
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Sequential Multiplier
Multiplication
begins with the
start pulse.
An add-and-shift
Sequential
Multiplier
When both bytes
are outputed.
done
start
Multiplier
Clk
lsb-out
msb-out
datapath
 Multiplier Block Diagram
For the most-significant
byte
An 8-bit bidirectional I/O
for inputing it’s 8-bit operands
and outputing its 16-bit output
one byte at a time.
Verilog Digital System Design
Z. Navabi, 2006
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Sequential Multiplier
Sequential
Multiplier
Shift-and-add
Multiplication
Process
Sequential
Multiplier
Design
Verilog Digital System Design
Z. Navabi, 2006
Multiplier
Testing
13
Shift-and-add Multiplication Process
Sequential
Multiplier
Shift-and-add
Shift-and-add
Multiplication
Process
Process
Sequential
Multiplier
Design
Verilog Digital System Design
Z. Navabi, 2006
Multiplier
Testing
14
Shift-and-add Multiplication Process
Depending on bit i of
operand A, either operand
B is added to the collected
partial result and then
shifted to the right
(when bit i is 1)
B: 1 0 1 1 0 1 1 0
A: 1 0 0 1 0 1 0 0
00000000
00000000
10110110
00000000
10110110
00000000
00000000
10110110
Or (when bit i is 0) the
collected partial result
is shifted one place to
the right without being
added to B.
110100100111000
 Manual Binary Multiplication
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Shift-and-add Multiplication Process
t=0
P:
0
0
0
0
B:
1
1
0
1
A:
1
0
0
1
A and B
t=1
0000+1101
0
1
1
0
1
1
0
1
t=3
0011+0000
0
0
0
1
1
1
0
1
01101
1
1
t=2
0
0
00011
1
0
0110+0000
0
0
1
1
1
1
0
1
t=4
1
1
0
0001+1101
0
1
1
1
1
1
0
1
00110
1
1
0
0
1
01110
0
1
Result
 Hardware Oriented Multiplication Process
Verilog Digital System Design
Z. Navabi, 2006
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Shift-and-add Multiplication Process
t=0
P:
0
0
0
0
A:
1
0
0
1
B:
1
1
0
1
Because A[0] is 1, the partial
sum of B + P is calculated.
A and B
 Hardware Oriented Multiplication Process (Continued)
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Shift-and-add Multiplication Process
t=1
0000+1101
0
1
1
0
1
1
0
1
t=2
0110+0000
0
1
0
1
1
0
1
1
01101
1
1
0
0
Because A[0] is 0,
0000 + P is calculated
00110
0
1
1
0
The right most bit of
which is shifted into A,
and the rest replace P
 Hardware Oriented Multiplication Process (Continued)
Verilog Digital System Design
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Shift-and-add Multiplication Process
t=3
0011+0000
0
0
0
1
1
1
0
1
t=4
0001+1101
0
1
1
1
00011
1
0
1
1
0
1
01110
0
1
The least significant 4 bits of
1 1 0 1 Result
the multiplication result
become available in A and the
 Hardware Oriented Multiplication Process (Continued)
most-significant bits in P.
Verilog Digital System Design
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Sequential Multiplier Design
Sequential
Multiplier
Shift-and-add
Multiplication
Process
Sequential
Sequential
Multiplier
Design
Design
Verilog Digital System Design
Z. Navabi, 2006
Multiplier
Testing
20
Sequential Multiplier Design
Sequential
Multiplier Design
Control Data
Partitioning
Multiplier
Datapath
Datapath
Description
Multiplier
Controller
Top-Level Code
of the Multiplier
Verilog Digital System Design
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Control Data Partitioning
Sequential
Multiplier Design
Control Data
Partitioning
Multiplier
Datapath
Datapath
Description
Multiplier
Controller
Top-Level Code
of the Multiplier
Verilog Digital System Design
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Control Data Partitioning
Data part consists of
registers, logic units, and
their interconnecting buses.
lsb_out
msb_out
Datapath
databus
8
clr_P
load_P
load_B
msb_out
lsb_out
sel_sum
load_A
shift_A
done
A0
start
 Datapath and Controller
Verilog Digital System Design
Z. Navabi, 2006
On the rising edge of the
system clock, the controller
goes into a new state.
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Multiplier Datapath
Sequential
Multiplier Design
Control Data
Partitioning
Multiplier
Multiplier
Datapath
Datapath
Description
Multiplier
Controller
Top-Level Code
of the Multiplier
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Selects carry-out from
the adder or 0 depending
on the value of sel_sum
Multiplier Datapath
Adder
co
sel_sum
Multiplexer
data
B
sum
load_B
clk
clr_P
A
ShiftAdd
P
load_P
8-bit Registers
A0
load_A
shift_A
msb_out
ShiftAdd[0]
lsb_out
8-bit Shift Register
Tri-state Buffers
 Multiplier Block Diagram
Verilog Digital System Design
Z. Navabi, 2006
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Datapath Description
Sequential
Multiplier Design
Control Data
Partitioning
Multiplier
Datapath
Datapath
Description
Multiplier
Controller
Top-Level Code
of the Multiplier
Verilog Digital System Design
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Datapath Description
module datapath ( input clk, clr_P, load_P,
load_B, msb_out, lsb_out,
sel_sum, load_A, shift_A,
inout [7:0] data, output A0 );
wire [7:0] sum, ShiftAdd;
reg [7:0] A, B, P;
wire co;
...............................
...............................
 Datapath Verilog Code
Verilog Digital System Design
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Datapath DescriptionRepresents
register B
always @( posedge clk ) if (load_B) B <= data;
always @( posedge clk )
if (load_P) P <= {co&sel_sum, ShiftAdd[7:1]};
assign { co, sum } = P + B;
Represents register P
Represents
the partial result
the 8-bit for
adder
always @( posedge clk )
Implements the
case ( { load_A, shift_A } )
8-bit shift-register
2'b01 : A <= { ShiftAdd[0], A[7:1] };
for operand A
2'b10 : A <= data;
Shifts A contents
default : A <= A;
endcase
Loads A with data
 Datapath Verilog Code (Continued)
Verilog Digital System Design
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Datapath Description
...............................
assign A0 = A[0];
Multiplexer for
selection of sum or P
assign ShiftAdd = clr_P ? 8'h0 :
( ~sel_sum ? P : sum );
assign data = lsb_out ? A : 8'hzz;
assign data = msb_out ? P : 8'hzz;
endmodule
 Datapath Verilog Code (Continued)
Verilog Digital System Design
Z. Navabi, 2006
2 sets of tri-state buffers
driving the bidirectional
data bus of the datapath
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Multiplier Controller
Sequential
Multiplier Design
Control Data
Partitioning
Multiplier
Datapath
Datapath
Description
Multiplier
Controller
Top-Level Code
of the Multiplier
Verilog Digital System Design
Z. Navabi, 2006
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Datapath Description
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
`define
idle
init
m1
m2
m3
m4
m5
m6
m7
m8
rslt1
rslt2
4'b0000
4'b0001
4'b0010
4'b0011
4'b0100
4'b0101
4'b0110
4'b0111
4'b1000
4'b1001
4'b1010
4'b1011
The multiplier
The multiplier
waits forcontroller
is a loading
finite state
start while
A machine
that has 2 starting states,
Multiplier loads B
8 multiplication states,
and 2 ending states.
The multiplier performs
add-and-shift of P+B, or
P+0, depending on A0
States and
their binary assignments
The 2 halves of the result
are put on databus.
 Multiplier Control States
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Declares signals that
connect to datapath ports
Multiplier Controller
module controller ( input clk, start, A0,
output reg clr_P, load_P, load_B, msb_out,
lsb_out, sel_sum,
output reg load_A, Shift_A, done);
reg [3:0] current;
always block to issue
control signals and make
state transitions
always @ ( negedge clk ) begin
clr_P = 0; load_P = 0; load_B = 0; msb_out = 0;
lsb_out = 0;
sel_sum = 0; load_A = 0; Shift_A = 0; done = 0;
..................................
Eliminating unwanted
All control signal outputs
set to their
inactive
values.
are Verilog
Code
of Controller
latches that may be
generated by a synthesis
for
these outputs.
Verilog Digital tool
System
Design
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Multiplier Controller
The currently active state
of the machine
case ( current )
`idle :
if (~start) begin
current <= `idle;
done = 1;
end else begin
To clear the P register
current <= `init;
To Load A
load_A = 1; clr_P = 1; load_P = 1;
end
`init : begin
current <= `m1;
load_B = 1; end
 Verilog Code of Controller (Continued)
Verilog Digital System Design
Z. Navabi, 2006
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Multiplier Controller
...............................
`m1, `m2, `m3, `m4, `m5, `m6, `m6, `m7, `m8:
begin
current <= current + 1;
Shifting A
Loading P
Shift_A = 1; load_P = 1;
if (A0) sel_sum = 1;
Asserting sel_sum
end
...............................
 Verilog Code of Controller (Continued)
Verilog Digital System Design
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Multiplier Controller
`rslt1 : begin
current <= `rslt2;
lsb_out = 1;
end
`rslt2 : begin
current <= `idle;
msb_out = 1;
end
default : current <= `idle;
endcase
end
endmodule
In the result states,
lsb_out and
msb_out
are asserted in two
consecutive clocks
in
order to put A and P
on the data bus
respectively.
 Verilog Code of Controller (Continued)
Verilog Digital System Design
Z. Navabi, 2006
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Top-Level Code of the Multiplier
Sequential
Multiplier Design
Control Data
Partitioning
Multiplier
Datapath
Datapath
Description
Multiplier
Controller
Top-Level
Top-Level Code
of
the Multiplier
Multiplier
of the
Verilog Digital System Design
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Top-Level Code of the Multiplier
module Multiplier ( input clk, start,
inout [7:0] databus,
output lsb_out, msb_out, done );
wire clr_P, load_P, load_B, msb_out, lsb_out,
sel_sum, load_A, Shift_A;
datapath dpu( clk, clr_P, load_P, load_B,
msb_out, lsb_out, sel_sum, load_A,
Shift_A, databus, A0 );
controller cu( clk, start, A0, clr_P, load_P,
load_B, msb_out, lsb_out,
sel_sum,
load_A, Shift_A, done
);
Datapath and controller
endmodule
 Top-Level Multiplier Code
modules are instantiated.
Verilog Digital System Design
Z. Navabi, 2006
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Multiplier Testing
Sequential
Multiplier
Shift-and-add
Multiplication
Process
Sequential
Multiplier
Design
Verilog Digital System Design
Z. Navabi, 2006
Multiplier
Testing
Testing
38
Multiplier Testing
timescale 1ns/100ps
An auto-check
interactive testbench for
the sequential multiplier
A bidirectional bus,
declared as wire for reading
module test_multiplier;
reg clk, start, error;
wire [7:0] databus;
wire lsb_out, msb_out, done;
reg [7:0] mem1[0:2], mem2[0:2];
reg [7:0] im_data, opnd1, opnd2;
reg [15:0] expected_result, multiplier_result;
integer indx;
Declared for writing to the
What
is calculated
The result read
...............................
Inputs and outputs
bidirectional databus
in
the
testbench
from
the
multiplier
...............................
of
the multiplier
 Multiplier Testbench Outline
Verilog Digital System Design
Z. Navabi, 2006
39
Multiplier Testing
Read data files data1.dat
...............................
and data2.dat and apply
Multiplier uut ( clk, start, databus,
lsb_out,
data
to databus
Apply
start
to start
msb_out, done
); the
multiplication
Calculate
Wait//Figure
for multiplication
to
initial begin: Apply_data
... end
8.11
expected
result
complete, and collect the
initial begin: Apply_Start ... end //Figure
8.12
calculated
result
Compare expected and
initial begin: Expected_Result... end //Figure8.13
calculated results and issue
always @(posedge clk) begin: Actual_Result
end
error if they do ...
not match
// Figure 8.14
always @(posedge clk) begin: Compare_Results...end
// Figure 8.15
Above
tasksthree
are timed
Applies
rounds of test
always #50 clk = ~clk;
independently,
the same module.
time,
to theatMultiplier
assign databus=im_data;
an always
block
generates
In each
round,
data isa applied
endmodule
 Multiplier Testbench Outline
periodic
signal
on clk
that test and
to the
module
under
clocks
theare
multiplier.
results
read and compared
Verilog Digital System Design
Z. Navabi, 2006
with the expected results.
40
Multiplier Testing
Multiplier
Testing
Reading
Data Files
Applying
Start
Calculating
Expected Result
Reading
Multiplier Output
Comparing
Results
Verilog Digital System Design
Z. Navabi, 2006
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