Transcript 2’s Complement 4-Bit Saturator Lecture L4.6

2’s Complement 4-Bit Saturator
Lecture L4.6
Equality Detector
XNOR
X
Y
Z
Z = !(X $ Y)
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
1
Z = 1 if A=B=C
A
A=B
Z
A=B=C
B
C
B=C
Multiplexers
C0
C1
C2
C3
4x1
MUX
s1 s0
Y
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A multiplexer is a
digital switch
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0 1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A 2 x 1 MUX
A
2x1
MUX
B
Z
s0
Z
0
A
1
B
s0
Z = A & !s0 # B & s0
Problem
How would you make a
Quad 2-to-1 MUX?
[A3..A0]
[B3..B0]
Quad
2-to-1
MUX
S
[Y3..Y0]
S
Y
0
1
A
B
NASA Tech Briefs
November 2001
X = 011101
Y = 0111
X = 110101
Y = 1000
B
X0
X1
X2
X3
A
Y0
Y1
Y2
Y3
c0
X4
c1
X5
X = 111111
Y = 1111
X = 000101
Y = 0101
ABEL
//
//
//
//
//
//
//
Title: 2s-complement 4-bit Saturator
Author: R. E. Haskell
Ref:
NASA Tech Briefs, Nov. 2001
Description: 4-bit output Y =
-8 if 6-bit input X is <= -8
+7 if 6-bit input X is >= +7
X otherwise
MODULE sat64
INTERFACE ([X5..X0] -> [Y3..Y0]);
TITLE '2s complement 4-bit saturator'
//
Author: R. E. Haskell
DECLARATIONS
" Input Pins "
X5..X0 PIN ISTYPE 'com';
X = [X5..X0];
" Output Pins "
Y3..Y0 PIN ISTYPE 'com';
Y = [Y3..Y0];
"Definitions
A = [X5,!X5,!X5,!X5];
B = [X3,X2,X1,X0];
c0 = !(X3 $ X4);
c1 = !(X4 $ X5);
s = c0 & c1;
" 6-bit input
" 4-bit output
A
X0
X1
X2
X3
B
c0
X4
EQUATIONS
Y = !s & A # s & B;
END
X5
c1
Y0
Y1
Y2
Y3
Top-level Design
[LED13..LED16]
[DataIn]
6
4
4
sat
sat64
abs
absval
4
d7R
hex7seg
7
[a,b,c,d,e,f,g]
1
[gg]
//
//
//
//
Title:
Author:
Input:
Output:
Absolute value function
R. E. Haskell
Y = 4-bit signed number (-8 to +7)
Z = magnitude of input number (0 to 8)
MODULE absval
interface([Y3..Y0] -> [Z3..Z0]);
DECLARATIONS
" INPUT PINS "
Y3..Y0 PIN;
Y = [Y3..Y0];
" 4-bit input
" OUTPUT PINS "
Z3..Z0 PIN ISTYPE 'com';
Z = [Z3..Z0];
" 4-bit output
DECLARATIONS
" INPUT PINS "
Y3..Y0 PIN;
Y = [Y3..Y0];
" 4-bit input
" OUTPUT PINS "
Z3..Z0 PIN ISTYPE 'com';
Z = [Z3..Z0];
" 4-bit output
EQUATIONS
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
when (Y ==
END absval
0)
1)
2)
3)
4)
5)
6)
7)
8)
9)
^h0A)
^h0B)
^h0C)
^h0D)
^h0E)
^h0F)
then
then
then
then
then
then
then
then
then
then
then
then
then
then
then
then
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
^b0000;
^b0001;
^b0010;
^b0011;
^b0100;
^b0101;
^b0110;
^b0111;
^b1000;
^b0111;
^b0110;
^b0101;
^b0100;
^b0011;
^b0010;
^b0001;
Top-level Design
[LED13..LED16]
[DataIn]
6
4
4
sat
sat64
abs
absval
4
d7R
hex7seg
7
[a,b,c,d,e,f,g]
1
[gg]
// Title
: 2's Complement 4-Bit Saturator
// Author
: R. E. Haskell
// Description : 7-segment displays show the signed output
//
of the 2's complement 4-bit saturator
MODULE sat4bit
DECLARATIONS
sat64 INTERFACE ([X5..X0] -> [Y3..Y0]);
sat FUNCTIONAL_BLOCK sat64;
absval INTERFACE ([Y3..Y0] -> [Z3..Z0]);
abs FUNCTIONAL_BLOCK absval;
hex7seg INTERFACE ([D3..D0] -> [a,b,c,d,e,f,g]);
d7R FUNCTIONAL_BLOCK hex7seg;
" INPUT PINS "
SW5..SW0 PIN 6,5,4,3,2,1;
SW = [SW5..SW0];
" S6, Switches 3,4; S7, Switches 1-4
" OUTPUT PINS "
LEDR3..LEDR0 PIN 40,41,43,44 ISTYPE 'com';
LEDR = [LEDR3..LEDR0];
" LEDs 13-16
[a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com';
Rsegments = [a,b,c,d,e,f,g]; " Rightmost 7-segment digit
minus PIN 66 ISTYPE 'com'; " segment g of left 7seg display
[LED13..LED16]
EQUATIONS
sat.[X5..X0] = SW;
6
sat
[DataIn]
sat64
LEDR = sat.[Y3..Y0];
abs.[Y3..Y0] = sat.[Y3..Y0];
d7R.[D3..D0] = abs.[Z3..Z0];
Rsegments = d7R.[a,b,c,d,e,f,g];
minus = sat.Y3;
END
4
4
abs
absval
4
d7R
hex7seg
7
[a,b,c,d,e,f,g]
1
[gg]
Verilog
//
//
//
//
//
//
//
Title: 2s-complement 4-bit Saturator
Author: R. E. Haskell
Ref:
NASA Tech Briefs, Nov. 2001
Description: 4-bit output Y =
-8 if 6-bit input X is <= -8
+7 if 6-bit input X is >= +7
X otherwise
module sat64(X,Y);
input [5:0] X;
output [3:0] Y;
module sat64(X,Y);
input [5:0] X;
output [3:0] Y;
wire
wire
wire
wire
[3:0] Y;
c0, c1, s;
[3:0] A;
[3:0] B;
A
X0
X1
X2
X3
B
c0
X4
X5
c1
assign A[3] = X[5];
assign A[2:0] = {~X[5],~X[5],~X[5]};
assign B = {X[3],X[2],X[1],X[0]};
assign c1 = X[3] ~^ X[4];
assign c0 = X[4] ~^ X[5];
assign s = c0 & c1;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule
Y0
Y1
Y2
Y3
Top-level Design
[LED13..LED16]
[DataIn]
6
4
4
sat
sat64
abs
absval
4
d7R
hex7seg
7
[a,b,c,d,e,f,g]
1
[gg]
//
//
//
//
Title:
Author:
Input:
Output:
Absolute value function
R. E. Haskell
Y = 4-bit signed number (-8 to +7)
Z = magnitude of input number (0 to 8)
module absval(Y,Z);
input [3:0] Y;
output [3:0] Z;
reg [3:0] Z;
module absval(Y,Z);
input [3:0] Y;
output [3:0] Z;
reg [3:0] Z;
always @(Y)
case(Y)
0: Z
1: Z
2: Z
3: Z
4: Z
5: Z
6: Z
7: Z
8: Z
9: Z
'hA: Z
'hb: Z
'hC: Z
'hd: Z
'hE: Z
'hF: Z
default:
endcase
endmodule
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Z
4'b0000;
4'b0001;
4'b0010;
4'b0011;
4'b0100;
4'b0101;
4'b0110;
4'b0111;
4'b1000;
4'b0111;
4'b0110;
4'b0101;
4'b0100;
4'b0011;
4'b0010;
4'b0001;
= 4'b0000;
// 0
Top-level Design
[LED13..LED16]
[DataIn]
6
4
4
sat
sat64
abs
absval
4
d7R
hex7seg
7
[a,b,c,d,e,f,g]
1
[gg]
// Title
: 2's Complement 4-Bit Saturator
// Author
: R. E. Haskell
// Description : 7-segment displays show the signed output
//
of the 2's complement 4-bit saturator
module sat4bit(SW,LEDR,LEDG,AtoG,gg);
input [5:0] SW;
output [3:0] LEDR;
output [5:0]LEDG;
output [6:0] AtoG;
output gg;
module sat4bit(SW,LEDR,LEDG,AtoG,gg);
input [5:0] SW;
output [3:0] LEDR;
output [5:0]LEDG;
output [6:0] AtoG;
output gg;
wire
wire
wire
wire
wire
wire
[6:0]
[3:0]
[5:0]
gg;
[3:0]
[3:0]
AtoG;
LEDR;
LEDG;
Y;
Z;
[LED13..LED16]
[DataIn]
6
4
4
sat
sat64
4
d7R
hex7seg
7
[a,b,c,d,e,f,g]
1
assign LEDR = Y;
assign LEDG = SW;
assign gg = Y[3];
sat64 sat(.X(SW),.Y(Y));
hex7seg d7R(.D(Z),.AtoG(AtoG));
absval abs(.Y(Y),.Z(Z));
endmodule
abs
absval
[gg]