ECE 3450

Altera DE2 Board and Quartus II Software

M. A. Jupina, VU, 2014

Lecture Objective

An overview of the Altera DE2 board and the Quartus II software. Course projects will use the Altera FPLD boards as a platform to implement complicated digital systems.

With the Quartus II software, you will use a system design approach to create your designs.

References: 1. Fundamentals of Digital Logic, Sections 2.9, 2.10, 3.5 – 3.7, and Appendices A-E.

2. Document files at the course web site ECE 3450 M. A. Jupina, VU, 2012

The Altera DE2 Development Board

Figure 1.2

The Altera DE2 FPGA Development board.

M. A. Jupina, VU, 2012

ECE 3450

In-System Programming of the Altera Development Board

M. A. Jupina, VU, 2012

Connections Between the Pushbuttons, the LEDs, and the Altera FPGA

Figure 1.6

FPGA I/O connections to Pushbuttons (PB

x

) and LED: Right of center, active LOW LED output (i.e., UP1 and UP2 boards) or on far right active HIGH LED output (i.e., DE1, DE2, and UP3 boards). Note that a depressed pushbutton input will be LOW. ECE 3450 M. A. Jupina, VU, 2012

9V DC Power Supply Connector USB Blaster Port USB Device USB Host Mic In Mic Out Line In Video In XSGA Video Port Ethernet 10/100M Port RS-232 Port ECE 3450

Power ON/OFF Switch

24-bit Audio CODEC USB Host/Slave Controller PS/2 Port 27Mhz Oscillator XSGA 10-bit DAC Ethernet 10/100M Controller TV Decoder (NTSC/PAL) Altera EPCS 16 Configuration Device Altera USB Blaster Controller Chipset 50Mhz Oscillator RUN/PROG Switch for JTAG/AS Modes LCD 16x2 Module 8MB SDRAM

90nm Cyclone II FPGA with 35K LEs

SD Card Connector 88 7-SEG Display Module 88 8 8 8 8 18 Red LEDs 512KB SRAM 1MB Flash Memory (upgradable to 4MB) 8 Green LEDs IrDA Transceiver SMA Ext Clk 18 Toggle Switches 4 Push-button Switches

Figure 1.16

Altera DE2 board showing the Pushbutton and LED locations used in design (enclosed in dashed ellipses seen in bottom right).

M. A. Jupina, VU, 2012

Examples of Dedicated Pin-Outs on the DE2 Cyclone II Chip

Table 1.2 Hardwired I/O connections on the various FPGA boards in the design example.

I/O Device DE1 Pin DE2 Pin UP3 Pin UP2 & 1 Pin PB1 PB2 LED

R21 (Key1) T22 (Key2) R20(LEDR0) N23 (Key1) P23 (Key2) AE23(LEDR0) 62 (SW7) 48 (SW4) 56 (D3) 28 (FLEX PB1) 29 (FLEX PB2) 14 (7Seg Dec. pt.) ECE 3450 M. A. Jupina, VU, 2012

Required Installation

of Quartus II on Laptops  Go to the ECE3450 folder on the K:\ Drive. Download the executable file 91_quartus_free to your laptop’s hard drive. Install the Quartus II software.

 After Installation, run the Quartus II software. Go to the menu Tools, License Setup, and in the box for License File put the following [email protected] so that your laptop can find the license on the ECE server.

ECE 3450 M. A. Jupina, VU, 2014

Design Process for Schematic or VHDL Entry

Figure 1.2

The Altera DE2 FPGA Development board.

M. A. Jupina, VU, 2014 ECE 3450

ECE 3450 Design Implementation Methodology Create/Edit Schematic/VHDL Compiler repeat until no errors Create Simulation Waveforms Simulator Run simulation until functionally correct Timing Analysis?

Modify design until timing specs are met Program Device M. A. Jupina, VU, 2014

ECE 3450

Creating a New Quartus II Project

M. A. Jupina, VU, 2014

Setting the FPGA Device Type

DE2

Cyclone II EP2C35F672C6

Figure 1.9

Setting the FPGA Device Type. Settings shown are for the DE1 board.

The Cyclone II Chip resides on the DE2 Board.

ECE 3450 M. A. Jupina, VU, 2014

Creating the Top-Level Project Schematic Design File ECE 3450 M. A. Jupina, VU, 2014

ECE 3450 Selecting a New Symbol with the Symbol Tool M. A. Jupina, VU, 2014

Active Low OR-Gate Schematic Example with I/O Pins Connected ECE 3450 M. A. Jupina, VU, 2014

ECE 3450 Assigning Pins with the Assignment Editor M. A. Jupina, VU, 2014

Active Low OR-Gate Timing Simulation with Time Delays ECE 3450 M. A. Jupina, VU, 2014

ECE 3450 VHDL Entity Declaration Text M. A. Jupina, VU, 2014

ECE 3450 VHDL OR-Gate Model (with Syntax Error) M. A. Jupina, VU, 2014

ECE 3450 VHDL Compilation with a Syntax Error M. A. Jupina, VU, 2014

Timing Analyzer Showing Input to Output Timing Delays ECE 3450 M. A. Jupina, VU, 2014

Floorplan View Showing Internal FPGA Placement of OR Gate in LE and I/O Pins ECE 3450 M. A. Jupina, VU, 2014

ECE 3450 ORgate Design Symbol orgate inst M. A. Jupina, VU, 2014

Implementation of a Simple Processor Bus Clock

IE A R A

Data

S DATA S A S B S C S Y IE B R B

Multiplexer

Start

State Machine

IE A IE B IE C IE X IE Y S DATA S A S B S C S Y AddSub Done

ECE 3450

IE C R C IE X IE Y R X

ALU

R Y AddSub

M. A. Jupina, VU, 2014

ECE 3450 Altera Implementation of Simple Processor M. A. Jupina, VU, 2014

ECE 3450 An Example Design Illustrating the Mapping of Multi-Bit Connections M. A. Jupina, VU, 2014

ECE 3450 An Example with a LPM Device M. A. Jupina, VU, 2014

Lpm_counter0 MegaWizard Edit Window ECE 3450 M. A. Jupina, VU, 2014