Transcript The GAL16V8 PLD

Ring Counter
Discussion 11.3
Example 32
4-Bit Ring Counter
q3
D
q
clk
~q
clr
clk
clr
q2
D
q
clk
~q
clr
q1
D
q
clk
~q
clr
D
q
clk
~q
set
q0
q3
q2
q1
module ring4(
input wire clk,
input wire clr,
clk
output reg [3:0] q clr
);
//
4-bit Ring Counter
always @(posedge clk or posedge clr)
begin
if(clr == 1)
Note non-blocking assignment
q <= 1;
else
begin
q[3] <= q[0];
q[2:0] <= q[3:1];
end
end
endmodule
D
q
clk
~q
clr
D
q
clk
~q
clr
D
q
clk
~q
clr
D
clk
set
q
~q
q0
Aldec Active-HDL Simulation
Johnson Counter
q3
D
q
clk
~q
clr
clk
clr
q2
D
q
clk
~q
clr
q1
D
q
clk
~q
clr
D
q
clk
~q
clr
q0
module johnson4(
input wire clk,
input wire clr,
output reg [3:0] q
);
johnson4.v
//
4-bit Johnson Counter
always @(posedge clk or posedge clr)
begin
if(clr == 1)
q <= 0;
else
begin
q[3] <= ~q[0];
q[2:0] <= q[3:1];
end
end
endmodule
Johnson Counter
A Random Number Generator
q3
D
q
clk
~q
clr
clk
clr
q2
D
q
clk
~q
clr
q1
D
q
clk
~q
clr
D
q
clk
~q
set
q0
Q3
D
Q
Q2
D
CLK !Q
Q
Q1
D
CLK !Q
Q0
Q
D
CLK !Q
Q
CLK !Q
CLK
q3 q2 q1 q0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
q3 q2 q1 q0
1
8
C
E
F
7
B
5
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
A
D
6
3
9
4
2
1
module rand4(
input wire clk,
input wire clr,
output reg [3:0] q
);
rand4.v
//
4-bit Random number generator
always @(posedge clk or posedge clr)
begin
if(clr == 1)
q <= 1;
else
begin
q[3] <= q[3] ^ q[0];
q[2:0] <= q[3:1];
end
end
endmodule
A Random Number Generator
Clock Pulse
outp
inp
Q2
clk
Q1
Q0
module clk_pulse(
input wire clk;
input wire clr;
input wire inp;
output wire outp;
);
reg [2:0] Q;
//
clock pulse generator
always @(posedge clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
begin
Q[2] <= inp;
Q[1:0] <= Q[2:1];
end
end
assign outp = Q[2] & Q[1] & ~Q[0];
endmodule
clk_pulse.v
outp
inp
Q2
clk
Q1
Q0