Transcript PPT - Electrical and Computer Engineering

EE4271
VLSI Design
Dr. Shiyan Hu
Office: EERC 518
[email protected]
Introduction
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
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Class Time and Office Hour
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Class Time: MWF 16:05-16:55 (EERC 214)
Office Hours: MWF 15:00-16:00 or by appointment, office:
EERC 518
Textbook (required): Digital Integrated Circuits: A Design
Perspective, second edition, by Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic, Prentice Hall, 2003. or
CMOS VLSI Design: A Circuits and Systems Perspective, fourth
edition, by Neil H.E. Weste and David M. Harris, Addiuson
Wesley, 2009
Grading:
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
Homework
Midterm
Final
Lab
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Introduction
Course Website
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http://www.ece.mtu.edu/faculty/shiyan/EE4271Fall13.htm
Contact information of instructor
 Email: [email protected]
 EERC 518
 Instructor’s webpage: http://www.ece.mtu.edu/faculty/shiyan
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Introduction
What is this course all about?

Introduction to digital integrated circuits.
 CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation.
Combinatorial Circuits and Sequential circuits.
Computer-Aided Design.

What will you learn?
 Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
speed, power dissipation, cost, and reliability
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Introduction
Agenda
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Introduction: Issues in digital integrated circuit (IC)
design
Device: MOS Transistors
Wire: R, L and C
Fabrication process
CMOS inverter
Combinational logic structures
Sequential logic gates
Design methodologies
VLSI Computer-Aided Design
Timing/power optimizations on gate and interconnect
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Introduction
Introduction
 Why
is designing
digital ICs different
today than it was
before?
 What is the
challenge?
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Introduction
The Transistor Revolution
First transistor
Bell Labs, 1948
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Introduction
The First Integrated Circuit
First IC
Jack Kilby
Texas Instruments
1958
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Introduction
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
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Introduction
Intel 8080 Micro-Processor
1974
4500 transistors
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Introduction
Intel Pentium (IV) microprocessor
2000
42 million transistors
1.5 GHz
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Introduction
Modern Chip
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Introduction
Moore’s Law
In
1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
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Introduction
Moore’s law
Twice the
number of
transistors,
approximately
every two
years
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Introduction
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moore’s Law
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8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
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Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium® III
Pentium® II
Pentium® Pro
Pentium®
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
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Courtesy, Intel
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Introduction
ITRS Prediction
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Introduction
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
P6
Pentium® proc
386
286
0.1
8086
8080
8008
4004
8085
Transistors
on Lead Microprocessors double every 2 years
0.01
0.001
1970
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1980
1990
Year
Courtesy, Intel
2000
2010
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Introduction
Frequency
Not true
any more!
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
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Courtesy, Intel
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Introduction
Interconnects Dominate
Delay (psec)
300
250
Interconnect delay
200
150
100
Transistor/Gate delay
50
0
0.8
0.5
0.35 0.25
Technology generation (m)
Source: Gordon Moore, Chairman Emeritus, Intel Corp.
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Introduction
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
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© Digital
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Courtesy, Intel
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Introduction
Power is a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
Pentium® proc
100
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
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© Digital
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Courtesy, Intel
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Introduction
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
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Courtesy, Intel
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Introduction
Not Only Microprocessors
Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)
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Introduction
Many Chips
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Introduction
Challenges in Digital Design
• Ultra-high speed design
• Interconnect delay
• Reliability, Manufacturability
• Power Dissipation
• Time to market
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Introduction
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
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Courtesy, ITRS Roadmap
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Introduction
Computer-Aided Design

Every new generation can integrate 2x more
functions per chip
 Chip price does not increase significantly
 Cost of a function decreases by 2x
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However,
 Design engineering population does not double every
two years.
 How to design much more complex chips (with more
and more functions)?
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Great need for ultra-fast design methods
 Design Automation (Computer-Aided Design)
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Introduction
Design Abstraction Enables CAD
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
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Introduction
Design Metrics
 How
to evaluate performance of a
digital circuit (gate, block, …)?
 Speed (delay, operating frequency)
 Power dissipation
 Cost
– Design time
– Design effort
 Reliability
– Process, voltage and temperature variations
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Introduction
Cost of Integrated Circuits
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NRE (non-recurrent engineering) costs
 design time and effort to design layout and
mask
 one-time cost factor

Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area
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Introduction
NRE Cost is Increasing
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Introduction
Die Cost
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
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Introduction
Yield
No. of good chipsper wafer
Yield 
100%
T otalnumber of chipsper wafer
Wafercost
Die cost 
Dies per wafer Die yield
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Introduction
Defects
 defectsper unit area die area 
Yield  1 





 is approximately 3 in the current fabrication process
About 0.5-1 defect per cm2.
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Introduction
Some Examples (1994)
Chip
Metal Line
layers width
Wafer
cost
Def./ Area Dies/ Yield
cm2 mm2 wafer
Die
cost
386DX
2
0.90
$900
1.0
43
360
71%
$4
486 DX2
3
0.80
$1200
1.0
81
181
54%
$12
Power PC
601
4
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
3
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
3
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
3
0.70
$1700
1.6
256
48
13%
$272
Pentium
3
0.80
$1500
1.5
296
40
9%
$417
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Introduction
Summary

Digital integrated circuit design faces huge
challenges for the coming decades
 High speed
 Low power
 Short design time for highly complex circuit having
1 billion transistors
 Reliable under noise and variations

Purpose of the course
 Understand the basics of VLSI design
 Getting a clear perspective on the challenges and
potential solutions
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