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Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Manufacturing
Process
July 30, 2002
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Manufacturing
CMOS Process
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Manufacturing
A Modern CMOS Process
gate-oxide
TiSi2
AlCu
SiO2
Tungsten
poly
p-well
n+
SiO2
n-well
p+
p-epi
p+
Dual-Well Trench-Isolated CMOS Process
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Manufacturing
Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
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Vout2
M3
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Manufacturing
Its Layout View
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Manufacturing
The Manufacturing Process
For a great tour through the IC manufacturing process
and its different steps, check
http://www.fullman.com/semiconductors/semiconductors.html
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Manufacturing
Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
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spin, rinse, dry
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Manufacturing
Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
Si-substrate
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
Si-substrate
UV-light
Patterned
optical mask
(e) After etching
Exposed resist
Si-substrate
(c) Stepper exposure
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SiO
2
Si-substrate
(f) Final result after removal of resist
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Manufacturing
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
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Manufacturing
CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer
p+
SiN
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p-epi
SiO
2
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
p+
p+
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(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
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Manufacturing
CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
p
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(e) After n-well and
V
adjust implants
Tp
(f) After p-well and
V
adjust implants
Tn
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Manufacturing
CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants. These
steps also dope the polysilicon.
SiO
2
(i) After deposition of SiO
insulator and contact hole2etch.
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Manufacturing
CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al layer.
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.
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Manufacturing
Advanced Metallization
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Manufacturing
Advanced Metallization
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Manufacturing
Design Rules
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Manufacturing
3D Perspective
Polysilicon
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Aluminum
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Manufacturing
Design Rules
Interface between designer and process
engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width
 scalable design rules: lambda parameter
 absolute dimensions (micron rules)

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Manufacturing
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
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Representation
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Manufacturing
Layers in 0.25 mm CMOS process
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Manufacturing
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
3
Metal1
2
2
3
4
Metal2
3
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Manufacturing
Transistor
Transistor Layout
1
3
2
5
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Manufacturing
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
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Manufacturing
Select Layer
2
3
Select
2
1
3
3
2
Substrate
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5
Well
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Manufacturing
CMOS Inverter Layout
In
GND
VD D
A
A’
Out
(a) Layout
A
A’
n
p-substrate
+
n
+
p
Field
Oxide
(b) Cross-Section along A-A’
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Manufacturing
Layout Editor
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Manufacturing
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
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Manufacturing
Sticks Diagram
V DD
3
Out
In
1
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
GND
Stick diagram of inverter
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Manufacturing
Packaging
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Manufacturing
Packaging Requirements
 Electrical:
Low parasitics
 Mechanical: Reliable and robust
 Thermal: Efficient heat removal
 Economical: Cheap
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Manufacturing
Bonding Techniques
Wire Bonding
Substrate
Die
Pad
Lead Frame
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Manufacturing
Tape-Automated Bonding (TAB)
Sprocket
hole
Film + Pattern
Solder Bump
Die
Test
pads
Lead
frame
Substrate
(b) Die attachment using solder bumps.
Polymer film
(a) Polymer Tape with imprinted
wiring pattern.
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Manufacturing
Flip-Chip Bonding
Die
Solder bumps
Interconnect
layers
Substrate
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Manufacturing
Package-to-Board Interconnect
(a) Through-Hole Mounting
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(b) Surface Mount
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Manufacturing
Package Types
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Manufacturing
Package Parameters
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Manufacturing
Multi-Chip Modules
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Manufacturing