Transcript Diapositiva 1 - Micrel Lab @ DEIS

Manufacturing Process
http://www-micrel.deis.unibo.it/CEDLA
General info
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Date esami:
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Giugno
Luglio
Sito per le slide o il materiale delle
esercitazioni:
http://www-micrel.deis.unibo.it/CEDLA
 Tutor del corso: ing. Elisabetta Farella.
 Per contattare il tutor: [email protected]
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The MOS Transistor
Gate Oxyde
Gate
Source
Polysilicon
n+
Drain
n+
p-substrate
Bulk Contact
CROSS-SECTION of NMOS Transistor
Field-Oxyde
(SiO2)
p+ stopper
The MOS Transistor
Polysilicon
Aluminum
Cross-Section of CMOS Technology
A Modern CMOS Process
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Dual-well approach
Circuit Under Design – Symbolic
representation
VDD
VDD
M2
M4
Vout
Vin
M1
Vout2
M3
Its Layout View
The Manufacturing Process
Sliced wafers
The Silicon Wafer
Molten Silicon Bath and
Czochralski method
Seed crystal
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Single-crystal ingot
Diamond saw
Important metric: defect density of the base
material
10-30 cm diameters, 1mm thickness
Doping: 2x1021 impurities/m3
2:00 – 4:15
Clean Rooms
Photolithography
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1. Oxidation layering
2. Photoresist coating
3. Stepper exposure
4. Photoresist development and bake
5. Acid Etching
6. Spin, rinse, and dry
7. Various process steps
8. Photoresist removal (or ashing)
Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
spin, rinse, dry
Example: Patterning of SiO2
Chemical or plasma
etch
Hardened resist
SiO 2
Si-substrate
(a) Silicon base material
Photoresist
SiO 2
Si-substrate
Si-substrate
(d) After development and etching of resist,
chemical or plasma etch of SiO 2
Hardened resist
SiO2
(b) After oxidation and deposition
of negative photoresist
UV-light
Patterned
optical mask
Si-substrate
(e) After etching
Exposed resist
Si-substrate
(c) Stepper exposure
Done in parallel on
the entire wafer
SiO 2
Si-substrate
(f) Final result after removal of resist
Scaling is getting mask-based steps more and more challenging
Recurring processing step (1)
DIFFUSION and ION IMPLANTATION
Doping recurs many times. Two approaches:
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DIFFUSION IMPLANTATION: wafers in quartz tube
in a heated furnace (900-1100 °C);  dopants in gas diffuse
in the exposed surface vertically and horizontally.  more
dopants on the surface than deeper in the material
ION IMPLANTATION (+ annealing): dopants
introduced by directing a beam of purified ions over
semiconductor surface.  Ions accelerations  deepness
of penetration; Beam current and exposure time  dosage.
 lattice damage. Repair by ANNEALING step (heating
based)
The magnets used to
control the ion beam
A wafer handling tray
in ion implantation
Diffusion
furnace
Recurring processing step (2)
DEPOSITION
Repetitively, material is deposited over the wafer (buffering,
insulating, etc.). Different techniques depending on
materials
 Chemical vapor deposition (CVD): gas-phase reaction
with energy supplied by heat (850°C). Ex. Si3N4
 Chemical deposition: Silane gas over heated wafer coated
with SiO2 = Polysilicon non-crystalline amorphous material
 Sputtering for Alluminium interconnect layers. Alluminium
evaporated in vacuum, heated by electron-beam or ionbeam bombarding.
 … etc.
Recurring processing step (3)
ETCHING
To selectively form patterns (wires, contact holes)
 Wet etching – use of acid or basic solutions
 Dry or plasma etching – well defined directionality
(sharp vertical contours)
PLANARIZATION
To ensure a flat surface a chemical-mechanical
planarization (CMP) step is included before
deposition of extra-metal layer on top of insulating
SiO2
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer
p+
SiN
34
p-epi
SiO
2
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
p+
p+
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
p
(e) After n-well and
V
adjust implants
Tp
(f) After p-well and
V
adjust implants
Tn
CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants. These
steps also dope the polysilicon.
SiO
2
(i) After deposition of SiO
insulator and contact hole2etch.
CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al layer.
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.
Advanced Metallization
Advanced Metallization
Design Rules
3D Perspective
Polysilicon
Aluminum
Design Rules
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Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
 scalable design rules: lambda parameter
 absolute dimensions (micron rules)
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Representation
Layers in 0.25 mm CMOS process
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
3
Metal1
2
3
2
4
Metal2
3
Transistor
Transistor Layout
1
3
2
5
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
Select Layer
2
3
Select
2
1
3
3
2
Substrate
5
Well
CMOS Inverter Layout
In
GND
VD D
A
A’
Out
(a) Layout
A
A’
n
p-substrate
+
n
(b) Cross-Section along A-A’
+
p
Field
Oxide
Layout Editor
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
Sticks Diagram
V DD
3
Out
In
1
GND
Stick diagram of inverter
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
Packaging
Packaging Requirements
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Electrical: Low parasitics
Mechanical: Reliable and robust
Thermal: Efficient heat removal
Economical: Cheap
Size: small
Bonding Techniques
Wire Bonding
Substrate
Die
Pad
Lead Frame
Tape-Automated Bonding (TAB)
Sprocket
hole
Film + Pattern
Solder Bump
Die
Test
pads
Lead
frame
Substrate
(b) Die attachment using solder bumps.
Polymer film
(a) Polymer Tape with imprinted
wiring pattern.
Flip-Chip Bonding
Die
Solder bumps
Interconnect
layers
Substrate
Package-to-Board Interconnect
(a) Through-Hole Mounting
(b) Surface Mount
(SMD)
(c) Ball Grid Array
Package Types
Package Parameters
Multi-Chip Modules