Transcript No Slide Title

EE4271
VLSI Design
Dr. Shiyan Hu
Office: EERC 731
Manufacturing
Process
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
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Manufacturing
Silicon Wafer
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
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Manufacturing
N-Well Process
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Manufacturing
Dual-Well Process
Wires on the top
gate-oxide
TiSi2
AlCu
SiO2
Tungsten
poly
p-well
n+
SiO2
n-well
p+
p-epi
p+
Dual-Well Trench-Isolated CMOS Process
Transistors at bottom
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Manufacturing
Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
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Vout2
M3
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Manufacturing
Its Layout View
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Manufacturing
VLSI Design and Fabrication
Lithography
Process
Designed Chip
Layout
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Fabricated
Chip
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Manufacturing
Chip
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Manufacturing
Lithography System - Simple View
Illumination
source
Mask
Objective Lens
Aperture
Wafer
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Manufacturing
Photo-Lithography Process – Full View
Part of
layout
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
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spin, rinse, dry
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Manufacturing
An Example: Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
Si-substrate
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
Si-substrate
UV-light
Patterned
optical mask
(e) After etching
Exposed resist
Si-substrate
(c) Stepper exposure
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SiO
2
Si-substrate
(f) Final result after removal of resist
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Manufacturing
Manufacturing Process
Part of the layout is put on a mask (level), so
we have many masks.
 Each mask level corresponds to different
actions in the fabrication process
 Each mask level contains non-overlapping
polygons, but polygons from different masks
may overlap subject to max/min distance rules
 Minimum geometry (lambda) rule is used. The
overlap is defined using lambda rule.

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Manufacturing
An Example - I
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Manufacturing
An Example - II
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Manufacturing
An Example - III
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Manufacturing
An Example - IV
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Manufacturing
An Example - V
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Manufacturing
An Example - VI
Active (diffusion) contact
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Manufacturing
An Example - VII
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Manufacturing
General CMOS Process
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
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Manufacturing
Contact and Via

Contact:
 link metal with diffusion (active)
 Link metal with gate poly

Via:
 Link wire with wire
Overlapping two layers (diffusion, gate poly or
metal) and providing a contact hole filled with
metal
 Substrate Contact and Well Contact:

 Link substrate or well to supply voltage
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Manufacturing
CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer (extended layer)
p+
SiN
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p-epi
SiO
2
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
p+
p+
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(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
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Manufacturing
CMOS Process Walk-Through
SiO (field oxide)
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
p
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This implant will only
impact the area below
the gate oxide but not
gate oxide itself
(e) After n-well implants
(by adjusting well doping
in order to have more
donar impurities
such as phosphorus)
(f) After p-well implants
(by adjusting well doping
in order to have more
acceptor impurities
such as boron)
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Manufacturing
CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants.
SiO
2
(i) After deposition of SiO
insulator and contact hole2etch.
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Manufacturing
CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al metal
layer.
Interlayer dielectric
(between wire and
diffusion, between wire
and wire)
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second metal layer of Al.
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Manufacturing
CMOS
Polysilicon
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Aluminum
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Manufacturing
Metal
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Manufacturing
Challenge
Illumination
source
Mask
193nm
45nm
Objective Lens
Aperture
Wafer
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Manufacturing
Mask v.s. Printing
Layout
0.13µ
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0.25µ
What you
design is
NOT what
you90-nm
get!
0.18µ
65-nm
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Manufacturing
Motivation
 Chip
design cannot be fabricated
 Gap
– Lithography technology: 193nm wavelength
– VLSI technology: 45nm features
 Lithography induced variations
– Impact on timing and power

Even for 180nm technology, variations up to 20x in
leakage power and 30% in frequency were reported.
Technology node
130nm
90nm
Gate length (nm)
Tolerable variation (nm)
90
5.3
53
3.75
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2.5
28
2
Wavelength (nm)
248
193
193
193
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65nm 45nm
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Manufacturing
Gap: Lithography Tech. v.s. VLSI Tech.
193nm
28nm, tolerable
distortion: 2nm
Increasing gap 
Printability problem (and
thus variations) more
severe!
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Manufacturing
Design Rules
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Manufacturing
Design Rules
Interface between designer and process
engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width
 scalable design rules: lambda parameter
 absolute dimensions (micron rules)

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Manufacturing
Lambda Rule




Every distance in layout rules is specified by lambda
Given a process, lambda is set to a specific value.
 Process technology is defined using minimum line width. 0.25um
technology means minimum line width is 0.25um. Lambda=minimum
line width/2.
 For a 0.25um process, lambda=0.125um
In practice, scaling is often not linear, e.g., from technology A to B,
minimum line width shrink by 0.5, but it does not necessarily mean that
minimum poly-diffusion distance also shrinks by 0.5.
Industry usually uses micron rule and lambda rule is used only for
prediction/estimation of the impact of technology scaling to a design.
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Manufacturing
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
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Representation
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Manufacturing
Layers in 0.25 mm CMOS process
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Manufacturing
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
3
Metal1
2
2
3
4
Metal2
3
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Manufacturing
Transistor
Transistor Layout
1
3
2
5
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Manufacturing
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
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Manufacturing
Select Layer
2
3
Select
2
1
3
3
2
Substrate
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Well
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Manufacturing
CMOS Inverter Layout
In
GND
VD D
A
A’
Out
(a) Layout
A
A’
n
p-substrate
+
n
+
p
Field
Oxide
(b) Cross-Section along A-A’
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Manufacturing
Layout Editor
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Manufacturing
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
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Manufacturing
Some Packages
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Manufacturing
Wire Bonding (not printed)
Wire Bonding
Bond wire
Substrate
Die
Pad
Lead Frame
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Manufacturing
Imprinted Tape-Automated Bonding
Sprocket
hole
Disadvantage: Must place I/O
pins at the specific locations (i.e.,
around the boundary on the die).
Film + Pattern
Solder Bump
Die
Test
pads
Lead
frame
Substrate
(b) Die attachment using solder bumps.
Polymer film
(a) Polymer Tape with imprinted
wiring pattern.
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Manufacturing
Die
Flip-Chip Bonding
Solder bumps
Interconnect
layers
Substrate

Flip-Chip places connection across the chip
rather than around boundary.
 The bond wire is replaced with solder bump
balls directly placed on the die surface
 Chip is flipped upside down
 Carefully align to package
 Heat to melt solder bump balls
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Manufacturing