Transcript No Slide Title

EE5780 Advanced
VLSI ComputerAided Design
Dr. Shiyan Hu
Office: EERC 518
[email protected]
Introduction
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
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Class Time and Office Hour



Class Time: MWF 14:05-14:55 (EERC 216)
Office Hours: MWF 15:00-15:50 or by appointment, office:
EERC 518
Textbook (suggested)
 Handbook of Algorithms for Physical Design Automation, Charles J. Alpert,
Dinesh P. Mehta, Sachin S. Sapatnekar, CRC Press, 2008

Grading:
 Homework
 Project
 Exams
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Course Website


http://www.ece.mtu.edu/faculty/shiyan/EE5780Spring12.htm
Contact information of instructor
 Email: [email protected]
 EERC 518
 Instructor’s webpage: http://www.ece.mtu.edu/faculty/shiyan
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Introduction
 Why
is designing
digital ICs different
today than it was
before?
 What is the
challenge?
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Introduction
The Transistor Revolution
First transistor
Bell Labs, 1948
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The First Integrated Circuit
First IC
Jack Kilby
Texas Instruments
1958
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Intel 4004 Microprocessor
1971
1000 transistors
1 MHz operation
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Introduction
Intel 8080 Microprocessor
1974
4500 transistors
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Intel Pentium Microprocessor
2000
42 million transistors
1.5 GHz
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Introduction
Modern Chip
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Basic Components In VLSI Circuits
 Devices
 Transistors
 Logic gates and cells
 Function blocks
 Interconnects




Local interconnects
Global interconnects
Clock interconnects
Power/ground nets
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Introduction
CMOS transistors
3 terminals in CMOS transistors:
 G: Gate
 D: Drain
 S: Source
nMOS transistor/switch
X=1 switch closes (ON)
X=0 switch opens (OFF)
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pMOS transistor/switch
X=1 switch opens (OFF)
X=0 switch closes (ON)
Introduction
An Example: CMOS Inverter
+Vd
d
F=
X’
Logic symbol
X
X
F=
X’
GR
D
Transistor-level schematic
Operation:
 X=1  nMOS switch conducts (pMOS is open)
and draws from GRD  F=0
 X=0  pMOS switch conducts (nMOST is open)
and draws from +Vdd  F=1
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Introduction
Cross-Section of A Chip
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Moore’s Law
In
1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
Not true any more
Interconnect delay dominates
Variations
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Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
P6
Pentium® proc
386
286
0.1
8086
8080
8008
4004
8085
Transistors
on Lead Microprocessors double every 2 years
0.01
0.001
1970
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1990
Year
Courtesy, Intel
2000
2010
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ITRS Prediction
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Frequency
Not true
any more!
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
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Courtesy, Intel
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Introduction
Interconnects Dominate
Delay (psec)
300
250
Interconnect delay
200
150
100
Transistor/Gate delay
50
0
0.8
0.5
0.35 0.25
Technology generation (m)
Source: Gordon Moore, Chairman Emeritus, Intel Corp.
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Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
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Courtesy, Intel
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Introduction
Power is a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
Pentium® proc
100
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
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Introduction
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
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Introduction
Chip Thermal
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Introduction
VLSI Design Cycle
System Specification
e.g., Verilog
Functional Design
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
Logic Design and
Synthesis
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VLSI Design Cycle (cont.)
Physical Design
Fabrication
Packaging
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Physical Design
Given a circuit after logic synthesis, to convert it into a
layout (i.e., determine the physical location of each
gate and the interconnects between gates).
PD
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Nanoscale Challenges
 Interconnect-limited
designs
 Interconnect performance limitation
 Interconnect modeling complexity
 Interconnect reliability (signal integrity)
 Power
barrier
 High degree of on-chip integration
 Complexity and productivity
 System on a chip

Variations
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Robust Design For Variations

Variations
 The difference between the designed value and the actual
value

Robust design
 Mitigate or compensate for variations
 Robustness for lithography-induced variations
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Chip Design and Fabrication
Lithography
Process
Designed Chip
Layout
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Fabricated
Chip
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Introduction
Photo-Lithography Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
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spin, rinse, dry
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Introduction
Lithography System
Illumination
Mask
193nm
wavelength
45nm
features
Objective Lens
Aperture
Wafer
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Mask v.s. Printing
Layout
0.13µ
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0.25µ
What you
design is
NOT what
you90-nm
get!
0.18µ
65-nm
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Motivation
 Chip
design cannot be fabricated
 Gap
– Lithography technology: 193nm wavelength
– VLSI technology: 45nm features
 Lithography induced variations
– Impact on timing and power

Even for 180nm technology, variations up to 20x in
leakage power and 30% in frequency were reported.
Technology node
130nm
90nm
Gate length (nm)
Tolerable variation (nm)
90
5.3
53
3.75
35
2.5
28
2
Wavelength (nm)
248
193
193
193
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65nm 45nm
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Introduction
Gap: Lithography Tech. v.s. VLSI Tech.
193nm
28nm, tolerable
distortion: 2nm
Increasing gap 
Printability problem (and
thus variations) more
severe!
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Summary
CAD is necessary to design a chip with billion
transistors.
 Digital integrated circuit design challenges in
nanoscale regime

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


Timing
Power
Reliability
Short design turn-around time
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