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Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Introduction
July 30, 2002
EE141 Integrated
© Digital
Circuits2nd
1
Introduction
What is this book all about?
Introduction to digital integrated circuits.
CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design
methodologies.
What will you learn?
Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability
EE141 Integrated
© Digital
Circuits2nd
2
Introduction
Digital Integrated Circuits
Introduction: Issues in digital design
The CMOS inverter
Combinational logic structures
Sequential logic gates
Design methodologies
Interconnect: R, L and C
Timing
Arithmetic building blocks
Memories and array structures
EE141 Integrated
© Digital
Circuits2nd
3
Introduction
Introduction
Why
is designing
digital ICs different
today than it was
before?
Will it change in
future?
EE141 Integrated
© Digital
Circuits2nd
4
Introduction
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
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© Digital
Circuits2nd
5
Introduction
ENIAC - The first electronic computer (1946)
EE141 Integrated
© Digital
Circuits2nd
6
Introduction
The Transistor Revolution
First transistor
Bell Labs, 1948
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© Digital
Circuits2nd
7
Introduction
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
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© Digital
Circuits2nd
8
Introduction
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
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© Digital
Circuits2nd
9
Introduction
Intel Pentium (IV) microprocessor
EE141 Integrated
© Digital
Circuits2nd
10
Introduction
Moore’s Law
In
1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
EE141 Integrated
© Digital
Circuits2nd
11
Introduction
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moore’s Law
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© Digital
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
Circuits2nd
Introduction
12
Evolution in Complexity
EE141 Integrated
© Digital
Circuits2nd
13
Introduction
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium® III
Pentium® II
Pentium® Pro
Pentium®
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
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© Digital
Circuits2nd
Courtesy, Intel
14
Introduction
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
P6
Pentium® proc
386
286
0.1
8086
8080
8008
4004
8085
Transistors
on Lead Microprocessors double every 2 years
0.01
0.001
1970
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© Digital
Circuits2nd
1980
1990
Year
Courtesy, Intel
2000
2010
15
Introduction
Die Size Growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
286
386
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law
EE141 Integrated
© Digital
Circuits2nd
Courtesy, Intel
16
Introduction
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
EE141 Integrated
© Digital
Circuits2nd
Courtesy, Intel
17
Introduction
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
EE141 Integrated
© Digital
Circuits2nd
Courtesy, Intel
18
Introduction
Power will be a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
Pentium® proc
100
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
EE141 Integrated
© Digital
Circuits2nd
Courtesy, Intel
19
Introduction
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
EE141 Integrated
© Digital
Circuits2nd
Courtesy, Intel
20
Introduction
Not Only Microprocessors
Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)
EE141 Integrated
© Digital
Circuits2nd
21
Introduction
Challenges in Digital Design
DSM
1/DSM
“Macroscopic Issues”
“Microscopic Problems”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
?
EE141 Integrated
© Digital
Circuits2nd
…and There’s a Lot of Them!
22
Introduction
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
EE141 Integrated
© Digital
Circuits2nd
Courtesy, ITRS Roadmap
23
Introduction
Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But …
How to design chips with more and more functions?
Design engineering population does not double every
two years…
Hence, a need for more efficient design methods
Exploit different levels of abstraction
EE141 Integrated
© Digital
Circuits2nd
24
Introduction
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
EE141 Integrated
© Digital
Circuits2nd
D
n+
25
Introduction
Design Metrics
How
to evaluate performance of a
digital circuit (gate, block, …)?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
EE141 Integrated
© Digital
Circuits2nd
26
Introduction
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area
EE141 Integrated
© Digital
Circuits2nd
27
Introduction
NRE Cost is Increasing
EE141 Integrated
© Digital
Circuits2nd
28
Introduction
Die Cost
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
EE141 Integrated
© Digital
Circuits2nd
29
Introduction
Cost per Transistor
cost:
¢-per-transistor
1
0.1
Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
EE141 Integrated
© Digital
1985
Circuits2nd
1988
1991
1994
1997
2000
2003
2006
2009
30
2012
Introduction
Yield
No. of good chips per wafer
Y
100%
T otalnumber of chips per wafer
Wafercost
Die cost
Dies per wafer Die yield
wafer diameter/22 wafer diameter
Dies per wafer
die area
2 die area
EE141 Integrated
© Digital
Circuits2nd
31
Introduction
Defects
defectsper unit area die area
die yield 1
is approximately 3
die cost f (die area)4
EE141 Integrated
© Digital
Circuits2nd
32
Introduction
Some Examples (1994)
Chip
Metal Line
layers width
Wafer
cost
Def./ Area Dies/ Yield
cm2 mm2 wafer
Die
cost
386DX
2
0.90
$900
1.0
43
360
71%
$4
486 DX2
3
0.80
$1200
1.0
81
181
54%
$12
Power PC
601
4
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
3
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
3
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
3
0.70
$1700
1.6
256
48
13%
$272
Pentium
3
0.80
$1500
1.5
296
40
9%
$417
EE141 Integrated
© Digital
Circuits2nd
33
Introduction
Reliability―
Noise in Digital Integrated Circuits
v(t)
V DD
i(t)
Inductive coupling
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© Digital
Circuits2nd
Capacitive coupling
Power and ground
noise
34
Introduction
DC Operation
Voltage Transfer Characteristic
V(y)
V
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)
f
OH
V(y)=V(x)
VM Switching Threshold
V OL
V OL
V
OH
V(x)
Nominal Voltage Levels
EE141 Integrated
© Digital
Circuits2nd
35
Introduction
Mapping between analog and digital signals
V
“ 1”
V
OH
V
V
IH
out
Slope = -1
OH
Undefined
Region
V
“ 0”
V
Slope = -1
IL
V
OL
OL
V
EE141 Integrated
© Digital
Circuits2nd
IL
V
IH
V
in
36
Introduction
Definition of Noise Margins
"1"
V
OH
Noise margin high
NM H
V
IH
Undefined
Region
NM L
V
OL
V
IL
Noise margin low
"0"
Gate Output
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© Digital
Circuits2nd
Gate Input
37
Introduction
Noise Budget
Allocates
gross noise margin to
expected sources of noise
Sources: supply noise, cross talk,
interference, offset
Differentiate between fixed and
proportional noise sources
EE141 Integrated
© Digital
Circuits2nd
38
Introduction
Key Reliability Properties
Absolute noise margin values are deceptive
a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)
Noise immunity is the more important metric –
the capability to suppress noise sources
Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;
EE141 Integrated
© Digital
Circuits2nd
39
Introduction
Regenerative Property
Regenerative
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© Digital
Circuits2nd
Non-Regenerative
40
Introduction
Regenerative Property
v0
v1
v2
v3
v4
v5
v6
A chain of inverters
Simulated response
EE141 Integrated
© Digital
Circuits2nd
41
Introduction
Fan-in and Fan-out
N
Fan-out N
EE141 Integrated
© Digital
Circuits2nd
M
Fan-in M
42
Introduction
The Ideal Gate
V out
Ri =
Ro = 0
Fanout =
NMH = NML = VDD/2
g=
V in
EE141 Integrated
© Digital
Circuits2nd
43
Introduction
An Old-time Inverter
5.0
4.0
NM L
3.0
(V)
2.0
out
V
VM
NM H
1.0
0.0
EE141 Integrated
© Digital
Circuits2nd
1.0
2.0
3.0
V in (V)
4.0
5.0
44
Introduction
Delay Definitions
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45
Introduction
Ring Oscillator
T = 2 tp N
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Circuits2nd
46
Introduction
A First-Order RC Network
R
vin
vout
C
tp = ln (2) t = 0.69 RC
Important model – matches delay of inverter
EE141 Integrated
© Digital
Circuits2nd
47
Introduction
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t T
1 t T
Pave
p(t )dt
isupplyt dt
t
T t
T
EE141 Integrated
© Digital
Circuits2nd
48
Introduction
Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav tp
Energy-Delay Product (EDP) =
quality metric of gate = E tp
EE141 Integrated
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49
Introduction
A First-Order RC Network
Vdd
E0->1 = C LVdd2
R PMOS
A1
NETWORK
vAinN
NMOS
i
vout supply
CVLout
CL
NETWORK
T
E
01
= P t dt = V i
t dt = V
dd sup ply
dd
0
0
T
E
Vdd
T
T
= P
t dt = V
i
t dt =
ca p
cap
out ca p
0
0
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© Digital
Circuits2nd
0
C dV
= C V 2
L out
L
dd
Vdd
1
2
-C V
C L Vout dVout = -dd
2 L
0
50
Introduction
Summary
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
Understanding the design metrics that govern
digital design is crucial
Cost, reliability, speed, power and energy
dissipation
EE141 Integrated
© Digital
Circuits2nd
51
Introduction