Transcript Chapter 6
Designing Combinational Logic Circuits: Part2 Alternative Logic Forms: Ratio Logic Pass-Transistor Dynamic Logic EE141 Integrated © Digital Circuits2nd 1 Combinational Circuits Ratio Logic VDD Resistive Load VDD Depletion Load RL PDN VSS (a) resistive load PMOS Load VSS VT < 0 F In1 In2 In3 VDD F In1 In2 In3 PDN VSS (b) depletion load NMOS F In1 In2 In3 PDN VSS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS EE141 Integrated © Digital Circuits2nd 2 Combinational Circuits Ratio Logic VDD • N transistors + Load Resistive Load • V OH = V DD RL • V OL = F In1 In2 In3 RPN + RL • Assymetrical response PDN • Static power consumption VSS EE141 Integrated © Digital RPN Circuits2nd • tpL = 0.69 RLCL 3 Combinational Circuits Active Loads VDD Depletion Load VDD PMOS Load VT < 0 VSS F In1 In2 In3 PDN VSS depletion load NMOS EE141 Integrated © Digital Circuits2nd F In1 In2 In3 PDN VSS pseudo-NMOS 4 Combinational Circuits Pseudo-NMOS VDD A B C D F CL VOH = VDD (similar to complementary CMOS) V2 k 2 OL p V k V – V V – ------------- = -----– V n DD Tn OL DD Tp 2 2 V OL = VDD – V T 1 – kp 1 – ------ (assuming that V T = V Tn = VTp ) kn SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!! EE141 Integrated © Digital Circuits2nd 5 Combinational Circuits Pseudo-NMOS VTC 3.0 2.5 W/Lp = 4 Vout [V] 2.0 1.5 W/Lp = 2 1.0 0.5 W/Lp = 0.5 W/Lp = 1 W/Lp = 0.25 0.0 0.0 0.5 1.0 1.5 2.0 2.5 Vin [V] EE141 Integrated © Digital Circuits2nd 6 Combinational Circuits Improved Loads VDD M1 Enable M2 M1 >> M2 F A B C D CL Adaptive Load EE141 Integrated © Digital Circuits2nd 7 Combinational Circuits Even Better Noise Immunity VDD M1 VDD M2 Out A A B B Out PDN1 PDN2 VSS VSS Differential Cascode Voltage Switch Logic (DCVSL) EE141 Integrated © Digital Circuits2nd 8 Combinational Circuits DCVSL Example Out Out B B A B B A XOR-NXOR gate EE141 Integrated © Digital Circuits2nd 9 Combinational Circuits DCVSL Transient Response V olta ge [V] 2.5 AB 1.5 0.5 -0.5 0 EE141 Integrated © Digital Circuits2nd AB A,B 0.2 A,B 0.4 0.6 Time [ns] 0.8 1.0 10 Combinational Circuits Pass-Transistor Logic Inputs B Switch Out A Out Network B A • N transistors • No static consumption EE141 Integrated © Digital Circuits2nd 11 Combinational Circuits Example: AND Gate B A B F = AB 0 EE141 Integrated © Digital Circuits2nd 12 Combinational Circuits NMOS-Only Logic 3.0 In 1.5m/0.25m VDD x Out 0.5m/0.25m 0.5m/0.25m Voltage [V] In Out 2.0 x 1.0 0.0 0 0.5 1 1.5 2 Time [ns] EE141 Integrated © Digital Circuits2nd 13 Combinational Circuits NMOS-only Switch C = 2.5V C = 2.5 V M2 A = 2.5 V A = 2.5 V B B Mn CL M1 VB does not pull up to 2.5V, but 2.5V - VTN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) EE141 Integrated © Digital Circuits2nd 14 Combinational Circuits NMOS Only Logic: Level Restoring Transistor VDD VDD Level Restorer Mr B A Mn M2 X Out M1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem EE141 Integrated © Digital Circuits2nd 15 Combinational Circuits Restorer Sizing Voltage [V] 3.0 2.0 •Upper limit on restorer size •Pass-transistor pull-down can have several transistors in stack W/Lr =1.75/0.25 W/L r =1.50/0.25 1.0 W/Lr =1.0/0.25 0.0 0 100 EE141 Integrated © Digital 200 Circuits2nd W/L r =1.25/0.25 300 Time [ps] 400 500 16 Combinational Circuits Solution 2: Single Transistor Pass Gate with VT=0 VDD VDD 0V 2.5V VDD 0V Out 2.5V WATCH OUT FOR LEAKAGE CURRENTS EE141 Integrated © Digital Circuits2nd 17 Combinational Circuits Complementary Pass Transistor Logic A A B B Pass-Transistor Network F (a) A A B B B Inverse Pass-Transistor Network B B A F B B A A B F=AB A B F=A+B F=AB AND/NAND EE141 Integrated © Digital Circuits2nd A F=AÝ (b) A A B B F=A+B B OR/NOR A F=AÝ EXOR/NEXOR 18 Combinational Circuits Solution 3: Transmission Gate C A C A B B C C C = 2.5 V A = 2.5 V B CL C=0V EE141 Integrated © Digital Circuits2nd 19 Combinational Circuits Resistance of Transmission Gate 30 2.5 V Resistance, ohms Rn 20 Rn Rp 2.5 V Vou t Rp 0V 10 Rn || Rp 0 0.0 EE141 Integrated © Digital 1.0 Circuits2nd Vou t , V 2.0 20 Combinational Circuits Pass-Transistor Based Multiplexer S S S S VDD S A VDD M2 F S M1 B S GND In1 EE141 Integrated © Digital Circuits2nd In2 21 Combinational Circuits Transmission Gate XOR B B M2 A A F M1 M3/M4 B B EE141 Integrated © Digital Circuits2nd 22 Combinational Circuits Delay in Transmission Gate Networks 2.5 2.5 V1 In 2.5 Vi Vi-1 C 0 2.5 C 0 Vn-1 Vi+1 C 0 Vn C C 0 (a) Req Req V1 In Req Vi C Vn-1 Vi+1 C C Req Vn C C (b) m Req Req Req Req Req Req In C CC C C CC C (c) EE141 Integrated © Digital Circuits2nd 23 Combinational Circuits Delay Optimization EE141 Integrated © Digital Circuits2nd 24 Combinational Circuits Transmission Gate Full Adder P VDD Ci A P A A P B VDD Ci A P Ci VDD S Sum Generation Ci P B VDD A P Co Carry Generation Ci A Setup P Similar delays for sum and carry EE141 Integrated © Digital Circuits2nd 25 Combinational Circuits Dynamic Logic EE141 Integrated © Digital Circuits2nd 26 Combinational Circuits Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors EE141 Integrated © Digital Circuits2nd 27 Combinational Circuits Dynamic Gate Clk Clk Mp off Mp on Out In1 In2 In3 Clk CL PDN 1 Out ((AB)+C) A C B Me Clk off Me on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) EE141 Integrated © Digital Circuits2nd 29 Combinational Circuits Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL EE141 Integrated © Digital Circuits2nd 30 Combinational Circuits Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL EE141 Integrated © Digital Circuits2nd 31 Combinational Circuits Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock EE141 Integrated © Digital Circuits2nd 32 Combinational Circuits Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk Evaluate VOut Me Precharge Leakage sources Dominant component is subthreshold current EE141 Integrated © Digital Circuits2nd 33 Combinational Circuits Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic EE141 Integrated © Digital Circuits2nd 34 Combinational Circuits Issues in Dynamic Design 2: Charge Sharing Clk Mp Out A CL B=0 Clk Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness CA Me EE141 Integrated © Digital CB Circuits2nd 35 Combinational Circuits Charge Sharing Example Clk A A B B B Cc=15fF C C Ca=15fF Out CL=50fF !B Cb=15fF Cd=10fF Clk EE141 Integrated © Digital Circuits2nd 36 Combinational Circuits Charge Sharing VDD case 1) if V out < VTn VDD Clk Mp Mp Out Out CL A A == BB 00 Clk CL Ma Ma XX M Mb b Mee M EE141 Integrated © Digital a CC a CC bb Circuits2nd C L VDD = C L Vout t + Ca VDD – V Tn V X or Ca V out = Vout t – V DD = – -------- V DD – V Tn V X C L case 2) if V out > VTn C --------------------a - Vout = –V DD C + C a L 37 Combinational Circuits Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) EE141 Integrated © Digital Circuits2nd 38 Combinational Circuits Issues in Dynamic Design 3: Backgate Coupling Clk Mp A=0 Out1 =1 CL1 Out2 =0 CL2 In B=0 Clk Me Dynamic NAND EE141 Integrated © Digital Circuits2nd Static NAND 39 Combinational Circuits Backgate Coupling Effect 3 2 Out1 1 Clk 0 In Out2 2 Time, ns -1 0 EE141 Integrated © Digital Circuits2nd 4 6 40 Combinational Circuits Issues in Dynamic Design 4: Clock Feedthrough Clk Mp A Out CL B Clk Me EE141 Integrated © Digital Circuits2nd Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. 41 Combinational Circuits Clock Feedthrough Clock feedthrough Clk Out 2.5 In1 1.5 In2 In3 In & Clk 0.5 In4 Out Clk -0.5 0 0.5 Time, ns 1 Clock feedthrough EE141 Integrated © Digital Circuits2nd 42 Combinational Circuits Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) EE141 Integrated © Digital Circuits2nd 43 Combinational Circuits Cascading Dynamic Gates V Clk Clk Mp Mp Out1 Clk Me Out2 In In Clk Clk Me Out1 VTn V Out2 t Only 0 1 transitions allowed at inputs! EE141 Integrated © Digital Circuits2nd 44 Combinational Circuits Domino Logic Clk In1 In2 In3 Clk EE141 Integrated © Digital Mp 11 10 PDN Me Circuits2nd Out1 Clk Mp Mkp Out2 00 01 In4 In5 Clk PDN Me 45 Combinational Circuits Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Ini Inj PDN Ini Inj PDN Like falling dominos! EE141 Integrated © Digital Circuits2nd 46 Combinational Circuits Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort EE141 Integrated © Digital Circuits2nd 47 Combinational Circuits Designing with Domino Logic VDD VDD VDD Clk Mp Clk Mp Out1 Mr Out2 In1 In2 In3 PDN PDN In4 Can be eliminated! Clk Me Clk Me Inputs = 0 during precharge EE141 Integrated © Digital Circuits2nd 48 Combinational Circuits Footless Domino VDD Clk VDD Mp Clk Mp Out1 0 Clk 1 0 Outn 1 0 In2 0 Mp Out2 In1 1 VDD 1 0 In3 1 0 1 Inn 1 0 The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage EE141 Integrated © Digital Circuits2nd 49 Combinational Circuits Differential (Dual Rail) Domino off Mp Mkp Clk Out = AB 1 on Mkp 0 Clk Mp 1 A !A 0 Out = AB !B B Clk Me Solves the problem of non-inverting logic EE141 Integrated © Digital Circuits2nd 50 Combinational Circuits np-CMOS Clk In1 In2 In3 Mp 11 10 PDN Clk Me Out1 Clk Me In4 In5 PUN 00 01 Clk Mp Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN EE141 Integrated © Digital Circuits2nd 51 Combinational Circuits NORA Logic Clk In1 In2 In3 Mp 11 10 Out1 PDN Clk In4 In5 PUN Clk to other PDN’s WARNING: Very sensitive to noise! EE141 Integrated © Digital Me 00 01 Me Circuits2nd Clk Mp Out2 (to PDN) to other PUN’s 52 Combinational Circuits Homework 6 Design (in Sue) a CPL version of the 16-bit ripple adder using transistors from the AMI 0.6 process. Simulate in Hspice and measure the worst case delay and average power/MHz. 2. Design (in Sue and simulate) a Domino version of the same ripple adder – measure the w.c. delay and average power/MHz. (How do these designs compare to Static CMOS?) 1. EE141 Integrated © Digital Circuits2nd 53 Combinational Circuits