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Circuit Characterization
Feb 4, 2005
Basic Device Equations (p.51)
 Cutoff
region: Vgs  Vt
 Ids = 0
 Linear/non-saturation
region: 0<Vds<Vgs-Vt
 Ids = ((Vgs – Vt)Vds – Vds2/2)
 Due to –Vds2/2, it is not really linear unless is
Vds very small
 Saturation
region: 0<Vgs – Vt <Vds
 Ids = (Vgs – Vt)2/2
Terms
 Ids is drain-to-source current
 Vds is drain-to-source voltage
Vgs is gate-to-source voltage
 Vt is threshold voltage
  is MOS transistor gain factor

 =(/tox)(W/L), where  is carrier mobility,  is
gate oxide permittivity, tox is thickness of gate
oxide, W and L are gate width and length

Example on p. 53
Importance of Interconnect
Interconnect delay dominates gate delay
delay (ps)

45
40
35
30
25
Gate
Interconnect
(Al+SiO2)
Interconnect
(Cu+lowk)
Sum (Al+SiO2)
20
15
10
5
0
Sum (Cu+lowk)
850
500
350
250
180
technology
130
100
Wire Resistance

Basic formula R=(/t)(l/w)
l
t
w
  : resistivity
 t: thickness, fixed for a given technology and layer
number
 l: conductor length
 w: conductor witdh
Sheet Resistance

Simply R=(/t)(l/w)=Rs(l/w)
l
w
 Rs: sheet resistance Ohms/square, where t is the
metal thickness for that metal layer
 l: conductor length
 w: conductor witdh
Typical Rs (Ohm/sq)
Min
Typical
Max
M1, M2
0.05
0.07
0.1
M3, M4
0.03
0.04
0.05
Poly
15
20
30
Silicide
2
3
6
Diffusio
n
N-well
10
25
100
1000
2000
5000
Compute Resistance
 Partition
long wire into rectangles
 Count
the number of squares
((l1/w1)+(l2/w2)+(l3/w3))Rs
w1
l1
w2
l2
w3
l3
More Accurate Method
w1
w1
w2
Ratio=w1/w2
w2
Ratio
1
1.5
Rs
2.5
2.55
2
3
2.6
2.75
Ratio
1.5
Rs
2.1
2
3
4
2.25
2.5
2.65
Contact and Via
 Fixed
resistance for each type of
contact and via
 0.25 ohm to 10 ohms
 Could vary due to process variation
Capacitor
 A capacitor
is a device that can store an
electric charge by applying a voltage
 The capacitance is measured by the
ratio of the charge stored to the applied
voltage
 Capacitance is measured in Farads
3D Parasitic Capacitance

Given a set of conductors, compute the
capacitance between all pairs of conductors.
-
1V
+
+
+
+
-
+
-
- -
C=Q/V
2D Simplified Model
Area capacitance:
area overlap between
adjacent layers
 Coupling capacitance:
between side-walls on
the same layer
 Fringing capacitance:
between side-wall and
adjacent layers

m3
m2
m2
m1
m2
Wire Capacitance
 More
difficult due to multiple layers,
different dielectric, void, and conformal
=8.0
multiple
dielectric
m3
m3
=4.0
m2 =3.9 m2 m2
=4.1
m1
m2
void
m2 conformal
m1
2D Method
C
= Ca*(overlap area)
+Cc*(length of parallel run)
+Cf*(perimeter)
 Coefficients Ca, Cc and Cf are given by
the fab
 Cadence Dracula
 Fast but inaccurate
2.5D Method
 Consider
interaction between layer i
and layers i+1, i+2, i–1 and i–2
 Consider distance between
conductors on the same layer
 Cadence Silicon Ensemble
 Accuracy 50%
Library Based Methods
 Build
a library of tens of thousands of
patterns and compute capacitance for
each pattern
 Partition layout into blocks, and match
with the library
 Accuracy 20%
3D Methods
 Finite
difference/finite element method
 Most accurate, slowest
 Raphael
 Boundary
element method
 FastCap, Hicap
 Monte
Carlo random walk
 QuickCap