COMPACT SMALL-SIGNAL MODELLING OF MULTIPLE

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Transcript COMPACT SMALL-SIGNAL MODELLING OF MULTIPLE

COMPACT SMALL-SIGNAL
MODELLING OF MULTIPLEGATE MOSFETs UP TO RF
OPERATION
Benjamin Iñiguez*, Antonio Lázaro*, Oana Moldovan*, Bogdan
Nae* and Hamdy A. Hamid**
*Department of Electronic Engineering, Universitat Rovira i
Virgili, Tarragona, 43007 SPAIN. E-mail:
[email protected]
**Department of Electrical and Computer Engineering, McMaster
University, Hamilton, Ontario, Canada
Summary of the work performed
• Compact quasi-static models for symmetrical and assymetrical Double-Gate
(DG) MOSFETs, cylindrical Gate-All Around (GAA) MOSFETs derived from the
solution of the 1-D Poisson’s equation, leading to a unified charge control model
from which the expressions of current, charges and small-signal parameters are
obtained. This charge control model can also be applied to FinFETs.
• Analytical models of the short-channel effects obtained by solving the 2D/3D
Poisson equation with the assumption that the electrostatic potential can be
written as the sum of the solution of the 1D Poisson’s equation (the dominant
one) and a remaining 2D/3D solution obtained using adequate techniques. These
short-channel effect models are incorporated into the general models
• The charge control model can account for quantum confinement by using a
corrected oxide capacitance which depends on the inversion centroid position,
written in terms of the inversion charge
• Extension of the models to the high frequency and noise analysis using the
active transmission line approach, considering also the gate tunneling noise
source. Both drift-diffusion and hydrodinamic transport were considered
Results
10
3
10
2
T
f (GHz)
Classical Drift-Diffusion
Classical Temperature Model
Quantum Drift-Diffusion
Quantum Temperature Model
10
Normalized CGD (a, c) and CGS (b, d) with respect
to the gate voltage, for VDS=1V (a, b) and VDS=0.1V (c, d).
Solid line: DESSIS-ISE simulations; Symbol line: analytical
model. Undoped DG MOSFET
1
0
50
100
Gate Length(nm)
150
200
Simulated fT versus gate length for FinFET
(Wfin=10 nm, Hfin=30 nm, tox=1.5 nm,
tbox=50 nm, Vds=1 V, Vgs-VTH=0.5V)